Datasheet > SI5375

SI5375

更新时间： 2024-11-08 01:21:59

品牌	Logo	应用领域
芯科 - SILICON		衰减器
页数	文件大小	规格书
54页	272K
描述
4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

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SI5375 数据手册

Si5375

4-PLL ANY-FREQUENCY PRECISION CLOCK

MULTIPLIER/JITTER ATTENUATOR

Features

 Highly integrated, 4–PLL clock  Integrated loop filter with

multiplier/jitter attenuator

programmable bandwidth as low

as 60 Hz

 Four independent DSPLLs

support any-frequency synthesis  Simultaneous free-run and

and jitter attenuation

synchronous operation

 Four inputs/four outputs

 Automatic/manual hitless input

clock switching

 Each DSPLL can generate any

frequency from 2 kHz to

808 MHz from a 2 kHz to

710 MHz input

 Selectable output clock signal

format (LVPECL, LVDS, CML,

CMOS)

Ordering Information:

See page 48.

 Ultra-low jitter clock outputs:

350 fs rms (12 kHz– 20 MHz)

and 410 fs rms (50 kHz–80 MHz)

typical

 LOL and interrupt alarm outputs

 I C programmable

 Single 1.8 V ±5% or 2.5 V ±10%

operation with high PSRR on-

chip voltage regulator

 Meets ITU-T G.8251 and

Telcordia GR-253-CORE OC-192

jitter specifications

 10x10 mm PBGA

Applications

 High density any-port, any-

protocol, any-frequency line

cards

 1/2/4/8/10G Fibre Channel

 GbE/10GbE Synchronous Ethernet

 Carrier Ethernet, multi-service

 ITU-T G.709 OTN custom FEC

 10/40/100G

switches and routers

 MSPP, ROADM, P-OTS,

 OC-48/192, STM-16/64

muxponders

Description

The Si5375 is a highly-integrated, 4-PLL, jitter-attenuating precision clock

multiplier for applications requiring sub 1 ps jitter performance. Each of the

DSPLL^®clock multiplier engines accepts an input clock ranging from 2 kHz to

710 MHz and generates an output clock ranging from 2 kHz to 808 MHz. The

device provides virtually any frequency translation combination across this

operating range. For asynchronous, free-running clock generation

applications, the Si5375’s reference oscillator can be used as a clock source

for any of the four DSPLLs. The Si5375 input clock frequency and clock

multiplication ratio are programmable through an I²C interface. The Si5375 is

based on Silicon Laboratories' third-generation DSPLL^®technology, which

provides any-frequency synthesis and jitter attenuation in a highly-integrated

PLL solution that eliminates the need for external VCXO and loop filter

components. Each DSPLL loop bandwidth is digitally-programmable,

providing jitter performance optimization at the application level. The device

operates from a single 1.8 or 2.5 V supply with on-chip voltage regulators with

excellent PSRR. The Si5375 is ideal for providing clock multiplication and

jitter attenuation in high port count optical line cards requiring independent

timing domains.

Rev. 1.0 8/12

Si5375

12 3 4 5 6 7...54

中文翻译

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与SI5375相关器件

型号	品牌	获取价格	描述	数据表
SI5375B-A-BL	SILICON	获取价格	Processor Specific Clock Generator, 808MHz, CMOS, PBGA80, 10 X 10 MM, PLASTIC, MO-192, BGA
SI5375B-A-GL	SILICON	获取价格	Processor Specific Clock Generator, 808MHz, CMOS, PBGA80, 10 X 10 MM, ROHS COMPLIANT, PLAS
SI5375-EVB	SILICON	获取价格	4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
SI5376	SILICON	获取价格	4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Si5376B-A-BL	SILICON	获取价格	4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Si5376B-A-GL	SILICON	获取价格	4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Si5376-EVB	SILICON	获取价格	4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
SI5380	SILICON	获取价格	Ultra-Low Phase Noise, 12-output JESD204B Clock Generator
SI5380_16	SILICON	获取价格	Ultra-Low Phase Noise, 12-output JESD204B Clock Generator
SI5380A-B-GM	SILICON	获取价格	Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

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