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SI5323-B-GMR PDF预览

SI5323-B-GMR

更新时间： 2024-11-19 13:13:31
品牌 Logo 应用领域
芯科 - SILICON 衰减器时钟
页数 文件大小 规格书
16页 648K
描述
Support Circuit, 1-Func, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36

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SI5323-B-GMR 技术参数

生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN,针数：36
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.8JESD-30 代码：S-XQCC-N36
长度：6 mm功能数量：1
端子数量：36最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE认证状态：Not Qualified
座面最大高度：0.9 mm标称供电电压：1.8 V
表面贴装：YES电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：INDUSTRIAL端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
宽度：6 mmBase Number Matches：1

SI5323-B-GMR 数据手册

 浏览型号SI5323-B-GMR的Datasheet PDF文件第2页浏览型号SI5323-B-GMR的Datasheet PDF文件第3页浏览型号SI5323-B-GMR的Datasheet PDF文件第4页浏览型号SI5323-B-GMR的Datasheet PDF文件第5页浏览型号SI5323-B-GMR的Datasheet PDF文件第6页浏览型号SI5323-B-GMR的Datasheet PDF文件第7页 
Si5323  
PRELIMINARY DATA SHEET  
PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR  
Description  
Features  
The Si5323 is a jitter-attenuating precision clock  
multiplier for high-speed communication systems,  
including SONET OC-48/OC-192, Ethernet, and Fibre  
Channel. The Si5323 accepts dual clock inputs ranging  
from 8 kHz to 707 MHz and generates two equal  
frequency-multiplied clock outputs ranging from 8 kHz  
to 1050 MHz. The input clock frequency and clock  
multiplication ratio are selectable from a table of  
popular SONET, Ethernet, and Fibre Channel rates.  
The Si5323 is based on Silicon Laboratories' 3rd-  
„ Selectable output frequencies ranging from 8 kHz to  
1050 MHz  
„ Ultra-low jitter clock outputs with jitter generation as  
low as 0.3 ps rms (50 kHz–80 MHz)  
„ Integrated loop filter with selectable loop bandwidth  
(60 Hz to 8.4 kHz)  
„ Meets OC-192 GR-253-CORE jitter specifications  
„ Dual clock inputs w/manual or automatically  
controlled hitless switching  
®
„ Dual clock outputs with selectable signal format  
generation DSPLL technology, which provides any-  
(LVPECL, LVDS, CML, CMOS)  
rate frequency synthesis and jitter attenuation in a  
highly integrated PLL solution that eliminates the need  
for external VCXO and loop filter components. The  
DSPLL loop bandwidth is digitally programmable,  
providing jitter performance optimization at the  
application level. Operating from a single 1.8, 2.5, or  
3.3 V supply, the Si5323 is ideal for providing clock  
multiplication and jitter attenuation in high performance  
timing applications.  
„ Support for ITU G.709 FEC ratios (255/238,  
255/237, 255/236)  
„ LOL, LOS alarm outputs  
„ Pin-controlled output phase adjust  
„ Pin-programmable settings  
„ On-chip voltage regulator for 1.8, 2.5, or 3.3 V  
±10% operation  
„ Small size: 6 x 6 mm 36-lead QFN  
„ Pb-free, ROHS compliant  
Applications  
„ SONET/SDH OC-48/OC-192 line cards  
„ GbE/10GbE, 1/2/4/8/10GFC line cards  
„ ITU G.709 line cards  
„ Optical modules  
„ Test and measurement  
Xtal or Refclock  
CKOUT1  
CKIN1  
®
Signal Format  
DSPLL  
CKOUT2  
CKIN2  
Disable/BYPASS  
Loss of Signal  
Loss of Lock  
Control  
Signal Detect  
VDD (1.8, 2.5, or 3.3 V)  
GND  
Frequency Select  
Bandwidth Select  
Rate Select  
Manua/l/Auto Switch  
Clock Select  
Latency Control  
Preliminary Rev. 0.2 3/07  
Copyright © 2007 by Silicon Laboratories  
Si5323  
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.  
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