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SI5324C-C-GM PDF预览

SI5324C-C-GM

更新时间: 2024-11-19 12:28:27
品牌 Logo 应用领域
芯科 - SILICON ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路衰减器异步传输模式时钟
页数 文件大小 规格书
72页 518K
描述
ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR

SI5324C-C-GM 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:QFN包装说明:6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36
针数:36Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:0.9
应用程序:SONET;SDHJESD-30 代码:S-XQCC-N36
长度:6 mm功能数量:1
端子数量:36最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:0.95 mm
标称供电电压:1.8 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6 mmBase Number Matches:1

SI5324C-C-GM 数据手册

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Si5324  
ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/  
JITTER ATTENUATOR  
Features  
Generates any frequency from  
2 kHz to 945 MHz and select  
frequencies to 1.4 GHz from an  
input frequency of 2 kHz to  
710 MHz  
Ultra-low jitter clock outputs as low  
as 290 fs rms (12 kHz–20 MHz),  
320 fs rms (50 kHz–80 MHz)  
Integrated loop filter with  
selectable loop bandwidth  
(4– 525 Hz)  
Freerun, Digital Hold operation  
Configurable signal format per  
output (LVPECL, LVDS, CML,  
CMOS)  
Support for ITU G.709 and custom  
FEC ratios (255/238, 255/237,  
255/236, 239/237, 66/64, 239/238,  
15/14, 253/221, 255/238)  
LOL, LOS, FOS alarm outputs  
I2C or SPI programmable  
On-chip voltage regulator with high  
PSNR  
Single supply 1.8 ±5%, 2.5 ±10%,  
or 3.3 V ±10%  
Meets ITU-T G.8251 and Telcordia  
GR-253-CORE jitter specification  
Hitless input clock switching with  
phase build-out  
Ordering Information:  
See page 63.  
Small size: 6 x 6 mm 36-lead QFN  
Pb-free, ROHS-compliant  
Pin Assignments  
Applications  
Broadcast video –3G/HD/SD-SDI, 1/2/4/8/10G Fibre Channel line  
Genlock cards  
Packet Optical Transport Systems GbE/10/40/100G Synchronous  
36 35 34 33 32 31 30 29 28  
RST  
NC  
1
2
3
4
5
6
7
8
9
27 SDI  
26  
(P-OTS), MSPP  
Ethernet (LAN/WAN)  
Data converter clocking  
Wireless base stations  
Test and measurement  
A2_SS  
25 A1  
INT_C1B  
C2B  
OTN/OTU-1/2/3/4 Asynchronous  
Demapping (Gapped Clock)  
SONET OC-48/192/768,  
SDH/STM-16/64/256 line cards  
24  
23  
A0  
GND  
Pad  
VDD  
XA  
SDA_SDO  
22 SCL  
XB  
21  
20  
CS_CA  
GND  
GND  
NC  
19 GND  
10 11 12 13 14 15 16 17 18  
Description  
The Si5324 is a low-bandwidth, jitter-attenuating, precision clock multiplier  
for applications requiring sub 1 ps jitter performance with loop bandwidths  
between 4 Hz and 525 Hz. The Si5324 accepts two input clocks ranging  
from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz  
to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided  
down separately from a common source. The Si5324 can also use its  
external reference as a clock source for frequency synthesis. The device  
provides virtually any frequency translation combination across this  
operating range. The Si5324 input clock frequency and clock multiplication  
ratio are programmable via an I2C or SPI interface. The Si5324 is based on  
Silicon Laboratories' 3rd-generation DSPLL® technology, which provides  
any-frequency synthesis and jitter attenuation in a highly integrated PLL  
solution that eliminates the need for external VCXO and filter components.  
The DSPLL loop bandwidth is digitally programmable, providing jitter  
performance optimization at the application level. The Si5324 is ideal for  
providing clock multiplication and jitter attenuation in high performance  
timing applications.  
Rev. 1.0 1/13  
Copyright © 2013 by Silicon Laboratories  
Si5324  

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