Datasheet > SI5324E-C-GMR

SI5324E-C-GMR

更新时间： 2024-11-19 19:44:11

品牌	Logo	应用领域
芯科 - SILICON		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
72页	2191K
描述
Support Circuit, 1-Func, QFN-36

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中文翻译

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技术参数
数据手册
替代型号

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SI5324E-C-GMR 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	QFN-36	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.29
JESD-30 代码：	S-XQCC-N36	长度：	6 mm
功能数量：	1	端子数量：	36
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	0.9 mm
标称供电电压：	1.8 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	6 mm	Base Number Matches：	1

SI5324E-C-GMR 数据手册

Si5324

ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/

JITTER ATTENUATOR

Features



Generates any frequency from

2 kHz to 945 MHz and select

frequencies to 1.4 GHz from an

input frequency of 2 kHz to

710 MHz

Ultra-low jitter clock outputs as low

as 290 fs rms (12 kHz–20 MHz),

320 fs rms (50 kHz–80 MHz)

Integrated loop filter with

selectable loop bandwidth

(4– 525 Hz)



Freerun, Digital Hold operation

Configurable signal format per

output (LVPECL, LVDS, CML,

CMOS)

Support for ITU G.709 and custom

FEC ratios (255/238, 255/237,

255/236, 239/237, 66/64, 239/238,

15/14, 253/221, 255/238)



LOL, LOS, FOS alarm outputs



I²C or SPI programmable

On-chip voltage regulator with high

PSNR

Single supply 1.8 ±5%, 2.5 ±10%,

or 3.3 V ±10%



Meets ITU-T G.8251 and Telcordia

GR-253-CORE jitter specification

Hitless input clock switching with

phase build-out

Ordering Information:



See page 64.



Small size: 6 x 6 mm 36-lead QFN

Pb-free, ROHS-compliant

Pin Assignments

Applications



Broadcast video –3G/HD/SD-SDI,  1/2/4/8/10G Fibre Channel line

Genlock cards

Packet Optical Transport Systems  GbE/10/40/100G Synchronous

36 35 34 33 32 31 30 29 28

RST

27 SDI

(P-OTS), MSPP

Ethernet (LAN/WAN)

Data converter clocking

Wireless base stations

Test and measurement

A2_SS

25 A1

INT_C1B

C2B

OTN/OTU-1/2/3/4 Asynchronous

Demapping (Gapped Clock)

SONET OC-48/192/768,

SDH/STM-16/64/256 line cards



GND

Pad

VDD

SDA_SDO

22 SCL

CS_CA

GND

19 GND

10 11 12 13 14 15 16 17 18

Description

The Si5324 is a low-bandwidth, jitter-attenuating, precision clock multiplier

for applications requiring sub 1 ps jitter performance with loop bandwidths

between 4 Hz and 525 Hz. The Si5324 accepts two input clocks ranging

from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz

to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided

down separately from a common source. The Si5324 can also use its

external reference as a clock source for frequency synthesis. The device

provides virtually any frequency translation combination across this

operating range. The Si5324 input clock frequency and clock multiplication

ratio are programmable via an I²C or SPI interface. The Si5324 is based on

Silicon Laboratories' 3rd-generation DSPLL^®technology, which provides

any-frequency synthesis and jitter attenuation in a highly integrated PLL

solution that eliminates the need for external VCXO and filter components.

The DSPLL loop bandwidth is digitally programmable, providing jitter

performance optimization at the application level. The Si5324 is ideal for

providing clock multiplication and jitter attenuation in high performance

timing applications.

Rev. 1.1 1/14

Si5324

12 3 4 5 6 7...72

中文翻译

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SI5324E-C-GMR 替代型号

型号	品牌	替代类型	描述	数据表
SI5324E-C-GM	SILICON	完全替代	Support Circuit, 1-Func, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36

与SI5324E-C-GMR相关器件

型号	品牌	获取价格	描述	数据表
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SI53254A-D02AMR	SILICON	获取价格	Processor Specific Clock Generator,
SI53258A-D01AM	SILICON	获取价格	Processor Specific Clock Generator,
SI5325A-B-GM	SILICON	获取价格	UP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER
SI5325A-B-GMR	SILICON	获取价格	暂无描述
SI5325A-C-GM	SILICON	获取价格	暂无描述
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SI5325B-B-GM	SILICON	获取价格	UP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

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