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SI5324

更新时间： 2024-11-19 09:25:59

品牌	Logo	应用领域
芯科 - SILICON		时钟
页数	文件大小	规格书
50页	336K
描述
Pin-Controlled 1_710 MHz Jitter Cleaning Clock

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中文翻译

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SI5324 数据手册

Si5317

PRELIMINARY DATA SHEET

PIN-CONTROLLED 1–710 MHZ JITTER CLEANING CLOCK

Features



Provides jitter attenuation on any

frequency

One clock input / two clock outputs

Input/output frequency range:

1–710 MHz



Selectable output clock signal

format: LVPECL, LVDS, CML or

CMOS

Single supply: 1.8, 2.5, or 3.3 V

VCO freeze during LOS/LOL

Loss of lock and loss of signal alarms

On-chip voltage regulator with high

PSRR



Ultra low jitter: 300 fs

(12 kHz–20 MHz) typical

Simple pin control interface

Selectable loop bandwidth for jitter

attenuation: 60 Hz–8.4 kHz



Small size: 6 x 6 mm, 36-QFN

Wide temperature range: –40 to

+85 ºC

Applications

Ordering Information:

See page 43.



Data converter clocking

Wireless infrastructure

Networking, SONET/SDH



Switches and routers

Medical instrumentation

Test and measurement

Pin Assignments

Description

The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications

that require jitter attenuation without clock multiplication. The Si5317 accepts a

single clock input ranging from 1 to 710 MHz and generates two low jitter clock

outputs at the same frequency. The clock frequency range and loop bandwidth are

selectable from a simple look-up table. The Si5317 is based on Silicon

Laboratories' 3rd-generation DSPLL^®technology, which provides jitter attenuation

on any frequency in a highly integrated PLL solution that eliminates the need for

external VCXO and loop filter components. The DSPLL loop bandwidth is user

selectable, providing jitter performance optimization at the application level.

36 35 34 33 32 31 30 29 28

RST

FRQTBL

LOS

27 FRQSEL3

FRQSEL2

25 FRQSEL1

FRQSEL0

BWSEL1

GND

Pad

VDD

22 BWSEL0

GND

DEC

INC

Functional Block Diagram

10 11 12 13 14 15 16 17 18

XTAL/Clock

Clock Out1

Clock In

DSPLL ^®

Signal Format [1:0]

Clock Out2

Status/Control

High

PSRR

Regulator

VDD (1.8, 2.5, 3.3 V)

GND

Frequency Table

Loss of Lock

Frequency Select [3:0]

Bandwidth Select [1:0]

Phase Skew INC/DEC

Loss of Signal

XTAL/Clock Rate [1:0]

Preliminary Rev. 0.15 4/10

Si5317

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

12 3 4 5 6 7...50

中文翻译

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与SI5324相关器件

型号	品牌	获取价格	描述	数据表
Si5324A-C-GM	SILICON	获取价格	ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR
Si5324B-C-GM	SILICON	获取价格	ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR
SI5324C-C-GM	SILICON	获取价格	ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR
Si5324D-C-GM	SILICON	获取价格	ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR
SI5324D-C-GMR	SILICON	获取价格	Support Circuit, 1-Func, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36
SI5324E-C-GM	SILICON	获取价格	Support Circuit, 1-Func, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36
SI5324E-C-GMR	SILICON	获取价格	Support Circuit, 1-Func, QFN-36
SI5325	SILICON	获取价格	UP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER
Si5325/26-EVB	SILICON	获取价格	ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
SI53254A-D01AMR	SILICON	获取价格	Processor Specific Clock Generator,

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