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SI5323-C-GMR PDF预览

SI5323-C-GMR

更新时间: 2024-11-19 21:10:43
品牌 Logo 应用领域
芯科 - SILICON ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
40页 1508K
描述
Support Circuit, 1-Func, QFN-36

SI5323-C-GMR 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:QFN包装说明:QFN-36
针数:36Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:1.76
应用程序:SONET;SDHJESD-30 代码:S-XQCC-N36
长度:6 mm功能数量:1
端子数量:36最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:0.9 mm
标称供电电压:1.8 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6 mmBase Number Matches:1

SI5323-C-GMR 数据手册

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Si5323  
PIN-PROGRAMMABLE PRECISION CLOCK  
MULTIPLIER/JITTER ATTENUATOR  
Features  
Pin-selectable output frequencies  
ranging from 8 kHz–708 MHz  
Ultra-low jitter clock outputs as low  
as 250 fs rms (12 kHz–20 MHz)  
270 fs rms (50 kHz–80 MHz)  
Integrated loop filter with selectable  
loop bandwidth (60 Hz–8.4 kHz)  
Meets ITU-T G.8251 and Telcordia  
OC-192 GR-253-CORE jitter  
specifications  
Dual clock outputs with selectable  
signal format (LVPECL, LVDS, CML,  
CMOS)  
Support for ITU G.709 FEC ratios  
(255/238, 255/237, 255/236)  
LOL, LOS alarm outputs  
Pin-controlled output phase adjust  
Single supply 1.8 ±5%, 2.5 or 3.3 V  
±10% operation with high PSRR  
On-chip voltage regulator  
Ordering Information:  
See page 33.  
Hitless input clock switching with  
phase build-out and digital hold  
Small size: 6 x 6 mm 36-lead QFN  
Applications  
Pin Assignments  
SONET/SDH OC-48/STM-16 and  
OC-192/STM-64 line cards  
GbE/10GbE, 1/2/4/8/10GFC line cards  
ITU G.709 line cards  
Optical modules  
Test and measurement  
Synchronous Ethernet  
36 35 34 33 32 31 30 29 28  
RST  
FRQTBL  
C1B  
1
2
3
4
5
6
7
8
9
27 FRQSEL3  
26  
Description  
FRQSEL2  
25 FRQSEL1  
C2B  
24  
23  
FRQSEL0  
BWSEL1  
The Si5323 is a jitter-attenuating precision clock multiplier for high-speed  
communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre  
Channel. The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz  
and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to  
1050 MHz. The input clock frequency and clock multiplication ratio are selectable  
from a table of popular SONET, Ethernet, and Fibre Channel rates. The Si5323 is  
based on Silicon Laboratories' 3rd-generation DSPLL® technology, which  
provides any-frequency synthesis and jitter attenuation in a highly integrated PLL  
solution that eliminates the need for external VCXO and loop filter components.  
The DSPLL loop bandwidth is digitally programmable, providing jitter performance  
optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V  
supply, the Si5323 is ideal for providing clock multiplication and jitter attenuation in  
high performance timing applications.  
GND  
Pad  
VDD  
XA  
22 BWSEL0  
XB  
21  
20  
19  
CS_CA  
INC  
GND  
DEC  
AUTOSEL  
10 11 12 13 14 15 16 17 18  
Functional Block Diagram  
Xtal or Refclock  
CKOUT1  
CKIN1  
®
Signal Format  
DSPLL  
CKOUT2  
CKIN2  
Disable/BYPASS  
Loss of Signal  
Loss of Lock  
Control  
Signal Detect  
VDD (1.8, 2.5, or 3.3 V)  
GND  
Frequency Select  
Bandwidth Select  
Rate Select  
Manual//Auto Switch  
Clock Select  
Skew Control  
Rev. 1.0 1/11  
Copyright © 2011 by Silicon Laboratories  
Si5323  

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