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SI4123-D-GT PDF预览

SI4123-D-GT

更新时间: 2024-11-01 11:49:31
品牌 Logo 应用领域
芯科 - SILICON 无线通信
页数 文件大小 规格书
36页 308K
描述
DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR WIRELESS COMMUNICATIONS

SI4123-D-GT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:2.22模拟集成电路 - 其他类型:PHASE LOCKED LOOP
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:7.8 mm功能数量:1
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Silver (Ag)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:4.4 mmBase Number Matches:1

SI4123-D-GT 数据手册

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Si4133  
Si4123/22/13/12  
DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS  
FOR WIRELESS COMMUNICATIONS  
FEATURES  
Dual-band RF synthesizers  
RF1: 900 MHz to 1.8 GHz  
RF2: 750 MHz to 1.5 GHz  
IF synthesizer  
Low phase noise  
Programmable powerdown modes  
1 µA standby current  
18 mA typical supply current  
2.7 to 3.6 V operation  
Packages: 24-pin TSSOP,  
28-lead QFN  
IF: 62.5 to 1000 MHz  
Integrated VCOs, loop filters,  
varactors, and resonators  
Minimal (2) number of external  
components required  
Ordering Information:  
Lead-free and RoHS compliant  
See page 31.  
Applications  
Pin Assignments  
Dual-band communications  
Digital cellular telephones GSM 850, E-GSM 900, DCS 1800,  
PCS 1900  
Digital cordless phones  
Analog cordless phones  
Si4133-GT  
SCLK  
SDATA  
GNDR  
RFLD  
1
2
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
SEN  
VDDI  
IFOUT  
GNDI  
3
Wireless local loop  
4
Description  
RFLC  
5
IFLB  
GNDR  
6
IFLA  
The Si4133 is a monolithic integrated circuit that performs both IF and dual-  
band RF synthesis for wireless communications applications. The Si4133  
includes three VCOs, loop filters, reference and VCO dividers, and phase  
detectors. Divider and powerdown settings are programmable with a three-  
wire serial interface.  
7
RFLB  
RFLA  
GNDD  
8
VDDD  
GNDD  
XIN  
9
GNDR  
GNDR  
RFOUT  
VDDR  
10  
11  
12  
PWDN  
AUXOUT  
Functional Block Diagram  
Si4133-GM  
Reference  
Amplifier  
XIN  
RFLA  
RFLB  
R  
R  
R  
Phase  
Detector  
RF1  
RF2  
IF  
Powerdown  
Control  
PWDN  
28 27 26 25 24 23  
22  
RFOUT  
N  
N  
N  
1
2
3
4
5
6
7
21  
20 IFLB  
19  
GNDR  
RFLD  
RFLC  
GNDR  
RFLB  
RFLA  
GNDR  
GNDI  
SDATA  
SCLK  
RFLC  
RFLD  
Serial  
Interface  
Phase  
Detector  
IFLA  
22-bit  
Data  
Register  
GND  
Pad  
SEN  
18 GNDD  
17 VDDD  
16  
GNDD  
Test  
Mux  
Phase  
Detector  
AUXOUT  
IFDIV  
IFOUT  
15 XIN  
8
9
10 11 12 13 14  
IFLA  
IFLB  
Patents pending  
Rev. 1.61 1/10  
Copyright © 2010 by Silicon Laboratories  
Si4133  

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