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SI4123G-BMR

更新时间: 2024-11-02 06:42:43
品牌 Logo 应用领域
芯科 - SILICON /
页数 文件大小 规格书
32页 702K
描述
RF and Baseband Circuit, MLP-28

SI4123G-BMR 技术参数

生命周期:Obsolete零件包装代码:DFN
包装说明:HVQCCN,针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84模拟集成电路 - 其他类型:PHASE LOCKED LOOP
JESD-30 代码:S-XQCC-N28长度:5 mm
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:-20 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
认证状态:Not Qualified座面最大高度:0.9 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
温度等级:OTHER端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
宽度:5 mm

SI4123G-BMR 数据手册

 浏览型号SI4123G-BMR的Datasheet PDF文件第2页浏览型号SI4123G-BMR的Datasheet PDF文件第3页浏览型号SI4123G-BMR的Datasheet PDF文件第4页浏览型号SI4123G-BMR的Datasheet PDF文件第5页浏览型号SI4123G-BMR的Datasheet PDF文件第6页浏览型号SI4123G-BMR的Datasheet PDF文件第7页 
Si4133G  
Si4123G/22G/13G/12G  
DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS  
FOR GSM AND GPRS WIRELESS COMMUNICATIONS  
Features  
Dual-band RF Synthesizers Fast settling time: 140 µs  
RF1: 900 MHz to 1.8 GHz  
RF2: 750 MHz to 1.5 GHz  
IF synthesizer: 500 to  
1000 MHz  
GPRS Class 12 compliant  
Low phase noise  
Si4133G-BT  
Programmable powerdown modes  
1 µA standby current  
Integrated VCOs, loop filters, 18 mA typical supply current  
varactors, and resonators 2.7 to 3.6 V operation  
Minimal number of external Packages: 24-pin TSSOP and  
Ordering Information:  
See page 28.  
components required  
28-pin MLP  
Applications  
Pin Assignments  
GSM 850, E-GSM 900, DCS 1800, and PCS 1900 cellular  
telephones  
Si4133G-BT  
GPRS data terminals  
HSCSD data terminals  
SEN  
SCLK  
SDATA  
GNDR  
RFLD  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VDDI  
2
Description  
IFOUT  
GNDI  
IFLB  
3
4
The Si4133G is a monolithic integrated circuit that performs both IF and  
dual-band RF synthesis for GSM and GPRS wireless communications  
applications. The Si4133G includes three VCOs, loop filters, reference  
and VCO dividers, and phase detectors. Divider and powerdown settings  
are programmable with a three-wire serial interface.  
RFLC  
5
IFLA  
GNDR  
RFLB  
6
GNDD  
VDDD  
GNDD  
XIN  
7
RFLA  
8
GNDR  
GNDR  
RFOUT  
VDDR  
9
10  
11  
12  
Functional Block Diagram  
PWDN  
AUXOUT  
Reference  
÷65  
XIN  
RFLA  
RFLB  
Phase  
Amplifier  
Detector  
RF1  
RF2  
IF  
Power  
Down  
Si4133G-BM  
PWDN  
RFOUT  
÷N  
÷N  
÷N  
Control  
SDATA  
SCLK  
RFLC  
RFLD  
Phase  
Serial  
28  
27  
26  
25  
24  
23  
22  
Interface  
Detector  
1
2
3
4
5
6
7
21  
20  
19  
18  
17  
16  
15  
GNDR  
RFLD  
RFLC  
GNDR  
RFLB  
RFLA  
GNDR  
GNDI  
IFLB  
22-bit  
Data  
SEN  
Register  
IFLA  
GND  
Pad  
Phase  
Test  
Mux  
GNDD  
VDDD  
GNDD  
XIN  
AUXOUT  
IFOUT  
Detector  
IFLA  
IFLB  
8
9
10  
11  
12  
13  
14  
Patents pending  
Rev. 1.4 5/03  
Copyright © 2003 by Silicon Laboratories  
Si4133G-DS14  

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