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SI4122G-BT PDF预览

SI4122G-BT

更新时间: 2024-11-11 03:32:07
品牌 Logo 应用领域
芯科 - SILICON 信号电路锁相环或频率合成电路光电二极管GSM无线
页数 文件大小 规格书
32页 468K
描述
DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR GSM AND GPRS WIRELESS COMMUNICATIONS

SI4122G-BT 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.7Is Samacsys:N
模拟集成电路 - 其他类型:PHASE LOCKED LOOPJESD-30 代码:R-PDSO-G24
长度:7.8 mm功能数量:1
端子数量:24最高工作温度:85 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES温度等级:OTHER
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

SI4122G-BT 数据手册

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Si4133G  
Si4123G/22G/13G/12G  
DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS  
FOR GSM AND GPRS WIRELESS COMMUNICATIONS  
Features  
Dual-Band RF Synthesizers Fast Settling Time: 140 µs  
RF1: 900 MHz to 1.8 GHz  
RF2: 750 MHz to 1.5 GHz  
IF Synthesizer  
Low Phase Noise  
Programmable Power Down Modes  
1 µA Standby Current  
Si4133G-BT  
IF: 500 MHz to 1000 MHz  
18 mA Typical Supply Current  
Integrated VCOs, Loop Filters, 2.7 V to 3.6 V Operation  
Varactors, and Resonators Packages: 24-Pin TSSOP and  
Minimal External Components  
Required  
Ordering Information:  
28-Pin MLP  
See page 28.  
Applications  
Pin Assignments  
GSM, DCS1800, and PCS1900 GPRS Data Terminals  
Cellular Telephones HSCSD Data Terminals  
Si4133G-BT  
Description  
SCLK  
SDATA  
GNDR  
RFLD  
SENB  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VDDI  
2
The Si4133G is a monolithic integrated circuit that performs both IF and  
dual-band RF synthesis for GSM and GPRS wireless communications  
applications. The Si4133G includes three VCOs, loop filters, reference and  
VCO dividers, and phase detectors. Divider and power down settings are  
programmable through a three-wire serial interface.  
IFOUT  
GNDI  
IFLB  
3
4
RFLC  
5
IFLA  
GNDR  
RFLB  
6
GNDD  
VDDD  
GNDD  
XIN  
7
RFLA  
8
Functional Block Diagram  
GNDR  
GNDR  
RFOUT  
VDDR  
9
10  
11  
12  
Reference  
Amplifier  
÷ 65  
XIN  
RFLA  
RFLB  
PWDNB  
AUXOUT  
Phase  
Detector  
RF1  
RF2  
IF  
Power  
Down  
PW DNB  
RFOUT  
÷ N  
÷ N  
÷ N  
Control  
Si4133G-BM  
SDATA  
SCLK  
RFLC  
RFLD  
Phase  
Serial  
Interface  
Detector  
22-bit  
Data  
SENB  
28  
27  
26  
25  
24  
23  
22  
Register  
1
2
3
4
5
6
7
21  
20  
19  
18  
17  
16  
15  
G NDR  
RFLD  
RFLC  
G NDR  
RFLB  
RFLA  
G NDR  
G NDI  
IFLB  
Phase  
Test  
Mux  
AUXOUT  
IFOUT  
Detector  
IFLA  
IFLA  
IFLB  
G NDD  
VDDD  
G NDD  
XIN  
8
9
10  
11  
12  
13  
14  
Patents pending  
Rev. 1.1 4/01  
Copyright © 2001 by Silicon Laboratories  
Si4133G-DS11  

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