GRAPHICS
S1D13505
S1D13505 Embedded RAMDAC LCD/CRT Controller
February 2009
■ DESCRIPTION
The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of CPUs and display
devices. The S1D13505 architecture is designed to meet the low cost, low power requirements of the embedded
markets, such as Mobile Communications, Hand-Held PCs, and Office Automation.
The S1D13505 supports multiple CPUs, all LCD panel types, CRT, and additionally provides a number of
differentiating features. Products requiring a “Portrait” mode display can take advantage of the SwivelView feature.
Simultaneous, Virtual and Split Screen Display are just some of the display modes supported, while the Hardware
Cursor, Ink Layer, and the Memory Enhancement Registers offer substantial performance benefits. These features,
combined with the S1D13505’s Operating System independence, make it an ideal display solution for a wide variety
of applications.
Display Modes
■ FEATURES
• 1/2/4/8/16 bit-per-pixel (bpp) support on LCD/CRT.
Memory Interface
• Up to 16 shades of gray using FRM on monochrome
• 16-bit EDO-DRAM or FPM-DRAM interface.
passive LCD panels.
• Memory size options:
• Up to 4096 colors on passive LCD panels.
512K bytes using one 256K×16 device.
• Up to 64K colors on active matrix TFT/D-TFD LCD
2M bytes using one 1M×16 device.
panels and CRT in 16 bpp modes.
• Addressable as a single linear address space.
CPU Interface
• Split Screen Display: allows two different images to be
simultaneously viewed on the same display.
• Supports the following interfaces:
• Virtual Display Support: displays images larger than the
Hitachi SH-4.
display size through the use of panning.
Hitachi SH-3.
Motorola M68K.
• Double Buffering/multi-pages: provides smooth
Philips MIPS PR31500/PR31700.
Toshiba MIPS TX3912.
Motorola Power PC MPC821.
NEC MIPS VR4102/VR4111.
Epson E0C33.
PC Card (PCMCIA).
StrongARM (PC Card).
ISA bus.
animation and instantaneous screen update.
• SwivelView: direct hardware 90° rotation of
display image for portrait mode display.
• Acceleration of screen updates by allocating full
display memory bandwidth to CPU.
• Hardware 64x64 pixel 2-bit cursor or full screen
2-bit ink layer.
Clo•ckSSinogulerccelock input for both pixel and memory clocks.
MPU bus interface with programmable READY.
• CPU write buffer.
Display Support
• Memory clock can be input clock or (input clock/2),
providing flexibility to use CPU bus clock as input.
• 4/8-bit monochrome passive LCD interface.
• Pixel clock can be memory clock or (memory clock/2) or
• 4/8/16-bit color passive LCD interface.
• Single-panel, single-drive displays.
• Dual-panel, dual-drive displays.
(memory clock/3) or (memory clock/4).
Power Down Modes
• Software power save mode.
• Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/D-TFD
• LCD power sequencing.
is supported up to 64K color depth (16-bit data).
General Purpose IO Pins
• Embedded RAMDAC with direct analog CRT drive.
• Up to 3 General Purpose IO pins are available.
• Simultaneous display of CRT and passive or TFT/D-TFD
Operating Voltage
panels.
• 2.7 volts to 5.5 volts.
Pac•ka1g2e8-pin QFP15 surface mount package.
• Maximum resolution of 800x600 pixels at a color
depth of 16 bpp.
X23A-C-002-15
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Revision 15.2