Datasheet > S1D13600F00A

S1D13600F00A

更新时间： 2024-09-19 20:47:27

品牌	Logo	应用领域
精工 - SEIKO		时钟外围集成电路
页数	文件大小	规格书
29页	190K
描述
CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64, QFP6-64

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S1D13600F00A 数据手册

S1D13600 Series

1. INTRODUCTION

Scope

This is the Functional Specification for S1D13600 3.3 V Ultra low Power LCD Controller Chip.

Objectives

(1) To specify functions and interface requirements of the chip.

(2) To allow review of the functions of the chip, as a preliminary specification.

2. FEATURES

Technology

•

ultra low power CMOS process

3.3 volt operation

chip supply with aluminum pad

64 pin QFP6 surface mount package

System

•

Direct connection to the 68 family CPUs.

minimum CPU Interface pin count.

no buffers are required in a 3.3 V-System.

internal oscillator with external Capacitance and Resistance, or external oscillator for a low frequency

input source.

•

interfaces to 64 kb and, or 256 kb SRAMs.

controls Seiko Epson’s RAM integrated Segment Drivers.

self-controlled Doze Mode.

optimized Hardware for low to medium resolution LCDs.

ultra low power consumption.

Rev. 2.3

EPSON

1–1

12 3 4 5 6 7...29

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型号	品牌	获取价格	描述	数据表
S1D13700	EPSON	获取价格	Embedded Memory Graphics LCD Controller
S1D13700F01	SEIKO	获取价格	640X240 DOTS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64, LEAD FREE, TQFP13-64
S1D13700F01A100	SEIKO	获取价格	IC,LCD CONTROLLER,TQFP,64PIN
S1D13700F02A100	EPCOS	获取价格	Hardware Functional Specification
S1D13700F02A100	SEIKO	获取价格	320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64, LEAD FREE, TQFP-64
S1D13704F00A	EPSON	获取价格	LCD Controller ICs
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