Datasheet > S1D13781F00A100

S1D13781F00A100

更新时间： 2024-11-08 19:55:55

品牌	Logo	应用领域
精工 - SEIKO		时钟外围集成电路
页数	文件大小	规格书
2页	135K
描述
800X480 PIXELS DOT MAT LCD DSPL CTLR, PQFP100, 14 X14 MM, 1.70 MM HEIGHT, QFP-100

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S1D13781F00A100 数据手册

GRAPHICS

S1D13781

S1D13781 WQVGA Graphics Controller

August 2009

The S1D13781 is a simple, multi-purpose Graphics LCD Controller with 384KByte embedded SRAM display

buffer which supports both RGB interface TFT and CSTN panels. The S1D13781 supports most popular CPU

interfaces in both 8/16-bit and Direct/Indirect variations. The embedded display buffer allows WQVGA up to

480x272 at 24bpp or 800x480 8bpp for single layer display, or 480x272 at 16bpp (Main Layer) and 480x272 at

8bpp (PIP Layer) for two layer display.

The S1D13781’s combination of multiple CPU interfaces and display interface types offers a versatile, yet easy to

develop display system. Additionally, it offers Multiple Window support, Transparency and Alpha Blending

functions, as well as 2D BitBLT functions. It is a flexible, low cost, low power, single chip solution designed to meet

the demands of embedded markets such as low end IP phone devices where total system cost and battery life

are major concerns. It’s impartiality to CPU type or operating system also makes it an ideal display solution for a

wide variety of other applications such as Office Automation and Factory Automation applications.

n FEATURES

• 384KByte Embedded Memory

• Direct and Indirect CPU Interfaces

• 8/16-bit data bus width

• General Purpose IO Pins

• LUT 256wordx24bitx3pcs for both Main and PIP

layer

• SPI CPU interface

• Alpha Blending, Transparency, Flashing

• 2D BitBLT

• Software initiated Power Save Mode

• H/PIOVDD: 3.3 or 1.8V, CORE/PLLVDD: 1.5V

• Clocks can be selected from embedded PLL or

digital clock inputs

• Support for single panel implementation:

- RGB Interface TFT panel

- Color and Monochrome STN

• Programmable resolutions (up to 800x480@8bpp)

and color depth (up to 24 bpp)

• Multiple Window (Layer) support for Main and PIP

• Rotation (Swivel View) 90°/180°/270°

• Temperature Range: -40° ~ 85°

• Package: QFP100-pin, 0.5mm pin pitch

n SYSTEM BLOCK DIAGRAM

TFT, CSTN

Control Signals

S1D13781

Host

CPU

S1D13781 Features

Embedded display buffer

2 layer support

Alpha Blending and Transparency

PIP layer Flashing

Programmable PLL

X94A-C-001-01

Revision 1.1

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