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S1D13700F01A100 PDF预览

S1D13700F01A100

更新时间: 2024-11-08 14:31:39
品牌 Logo 应用领域
精工 - SEIKO /
页数 文件大小 规格书
2页 94K
描述
IC,LCD CONTROLLER,TQFP,64PIN

S1D13700F01A100 数据手册

 浏览型号S1D13700F01A100的Datasheet PDF文件第2页 
LCD Controller  
S1D13700  
August 2007  
S1D13700 Embedded Memory Graphics LCD Controller  
The S1D13700 Embedded Memory Graphics LCD Controller can display both text and graphics on an LCD panel.  
The S1D13700 allows layered text and graphics, scrolling of the display in any direction, and partitioning of the  
display into multiple screens. It includes 32K bytes of embedded SRAM display memory which is used to store  
text, character codes, and bit-mapped graphics. The S1D13700 handles display controller functions including:  
transferring data from the controlling microprocessor to the buffer memory, reading memory data, converting data  
to display pixels, and generating timing signals for the LCD panel.  
The S1D13700 is designed with an internal character generator which supports 160, 5x7 pixel characters in  
internal mask ROM (CGROM) and 64, 8x8 pixel characters in character generator RAM (CGRAM). When the  
CGROM is not used, up to 256, 8x16 pixel characters are supported in CGRAM.  
Designed as a functional replacement to the S1D13305, the S1D13700 has an expanded feature set which  
includes; direct support of the Motorola MC68K microprocessor family, embedded display buffer, increased clock  
speeds, increased grayscale depths, lower power technology and smaller packages.  
FEATURES  
CPU Interface  
Display Modes  
8-bit CPU data bus interface  
Gray Shade Support for:  
1/2/4 bit-per-pixel (up to 16 gray shades)  
Direct Address Bus support for:  
Generic (Z80/8080 family) bus interface  
Motorola MC68K family bus interface  
Text, graphics, and combined text/graphics display  
modes  
Indirect Address Bus support for:  
Three overlapping screens in graphics mode  
Programmable cursor control (Hardware Cursor)  
Generic (Z80/8080 family) bus interface  
Motorola MC68K family bus interface  
Motorola M6800 family bus interface  
Smooth horizontal and vertical scrolling of all or part of  
the display  
Memory Interface  
Power  
Embedded 32K byte SRAM display buffer  
Software initiated Power Save Mode  
Low power consumption  
Display Support  
4-bit monochrome LCD interface  
Flexible Power Supply configuration:  
Programmable Display Resolutions:  
CORE VDD 3.0 to 3.6 volts.  
NIO VDD 3.0 to 5.5 volts (LCD interface).  
HIO VDD 3.0 to 5.5 volts (CPU interface).  
Typical resolutions include:  
640x240 at 1 bpp  
320x240 at 2 bpp  
Clock Source  
240x160 at 4 bpp  
Two terminal crystal or Single Oscillator input  
Input clock maximum of 60MHz  
1/2-duty to 1/256-duty LCD drive  
Character Generation  
Package  
160, 5x7 pixel characters in embedded mask-  
programmed character generator ROM  
TQFP13-64pin  
Up to 256, 8x16 pixel characters in embedded  
character generator RAM  
X42A-C-001-01  
1
Revision 1.01  

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