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PLL1705DBQR PDF预览

PLL1705DBQR

更新时间: 2024-11-07 22:26:27
品牌 Logo 应用领域
德州仪器 - TI 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
17页 128K
描述
3.3-V DUAL PLL MULTICLOCK GENERATOR

PLL1705DBQR 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SSOP
包装说明:0.150 INCH, GREEN, PLASTIC, MO-137AD, SSOP-20针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.64Is Samacsys:N
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:8.65 mm湿度敏感等级:1
端子数量:20最高工作温度:85 °C
最低工作温度:-25 °C最大输出时钟频率:36.864 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:27 MHz
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Clock Generators最大压摆率:25 mA
最大供电电压:3.6 V最小供电电压:2.7 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.64 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEOBase Number Matches:1

PLL1705DBQR 数据手册

 浏览型号PLL1705DBQR的Datasheet PDF文件第2页浏览型号PLL1705DBQR的Datasheet PDF文件第3页浏览型号PLL1705DBQR的Datasheet PDF文件第4页浏览型号PLL1705DBQR的Datasheet PDF文件第5页浏览型号PLL1705DBQR的Datasheet PDF文件第6页浏览型号PLL1705DBQR的Datasheet PDF文件第7页 
PLL1705  
PLL1706  
SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002  
3.3-V DUAL PLL MULTICLOCK GENERATOR  
FEATURES  
APPLICATIONS  
D
D
D
D
DVD Players  
D
D
27-MHz Master Clock Input  
Generated Audio System Clock:  
DVD Add-On Cards for Multimedia PCs  
Digital HDTV Systems  
Set-Top Boxes  
– SCKO0: 768 f (f = 44.1 kHz)  
S
S
– SCKO1: 384 f , 768 f (f = 44.1 kHz)  
S
S
S
– SCKO2: 256 f (f = 32, 44.1, 48, 64, 88.2,  
S
S
DESCRIPTION  
96 kHz)  
– SCKO3: 384 f (f = 32, 44.1, 48, 64, 88.2,  
The PLL1705 and PLL1706 are low cost, phase-locked  
loop (PLL) multiclock generators. The PLL1705 and  
PLL1706 can generate four system clocks from a 27-MHz  
reference input frequency. The clock outputs of the  
PLL1705can be controlled by sampling frequency-control  
pins and those of the PLL1706 can be controlled through  
serial-modecontrolpins. Thedevicegivescustomersboth  
cost and space savings by eliminating external  
components and enables customers to achieve the very  
low-jitterperformance needed for high performance audio  
DACs and/or ADCs. The PLL1705 and PLL1706 are ideal  
for MPEG-2 applications which use a 27-MHz master  
clock such as DVD players, DVD add-on cards for  
multimedia PCs, digital HDTV systems, and set-top  
boxes.  
S
S
96 kHz)  
D
D
D
Zero PPM Error Output Clocks  
Low Clock Jitter: 50 ps (Typical)  
Multiple Sampling Frequencies:  
– f = 32, 44.1, 48, 64, 88.2, 96 kHz  
S
D
D
3.3-V Single Power Supply  
PLL1705: Parallel Control  
PLL1706: Serial Control  
D
Package: 20-Pin SSOP (150 mil), Lead-Free  
Product  
FUNCTIONAL BLOCK DIAGRAM  
(ML)  
SR  
(MC) (MD)  
FS2  
FS1  
CSEL  
V
CC  
AGND  
V 1–3 DGND1–3  
DD  
ModeControl Interface  
Power Supply  
Reset  
PLL2  
XT1  
OSC  
XT2  
PLL1  
Divider  
Divider  
SCKO2  
Divider  
SCKO3  
MCKO1 MCKO2  
( ): PLL1706  
SCKO0  
SCKO1  
Pleasebe aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
The PLL1705 and PLL1706 use the same die and they are electrically identical except for mode control.  
PRODUCTION DATA information is current as of publication date. Products  
conform to specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all parameters.  
Copyright 2002, Texas Instruments Incorporated  

PLL1705DBQR 替代型号

型号 品牌 替代类型 描述 数据表
PLL1705DBQG4 TI

完全替代

3.3 V Dual PLL Multi-Clock Generator 20-SSOP -25 to 85
PLL1705DBQ TI

完全替代

3.3-V DUAL PLL MULTICLOCK GENERATOR

与PLL1705DBQR相关器件

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PLL1706DBQ TI

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PLL1706DBQ BB

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PLL1706DBQG4 BB

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PLL1706DBQG4 TI

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PLL1706DBQR BB

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PLL1706DBQRG4 BB

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