Datasheet > PLL1720A

PLL1720A

更新时间： 2024-11-09 21:55:27

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
2页	76K
描述
PHASE LOCKED LOOP

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数据手册

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PLL1720A 数据手册

PLL1720A

9939 Via Pasar • San Diego, CA 92126

TEL (858) 621-2700 FAX (858) 621-2722

PHASE LOCKED LOOP

Rev A1

PHASE NOISE (1 Hz BW, typical)

-40

-80

FEATURES

-120

1690 1760

MHz

• Frequency Range:

• Step Size:

KHz

-160

-200

•

- Style Package

PLL

APPLICATIONS

• Telecommunications

• Satellite

100 Hz

1 kHz

10 kHz

100 kHz

Telemetry

•

VALUE

1690 - 1760

2.5

UNITS

PERFORMANCE SPECIFICATIONS

Frequency Range

MHz

RMS Phase Error (100 Hz - 100 KHz)

Harmonic Suppression (2nd, typ.)

Sideband Spurs (typ.)

dBc

dBm

-15

-70

Power Output

3.5±2.5

Load Impedance

Step Size

KHz

HIGH

Charge Pump Output Current

Switching Speed (typ., adjacent channel)

Startup Lock Time (typ.)

mSec

°C

-40 to +85

Operating Temperature Range

Package Style

PLL

POWER SUPPLY REQUIREMENTS

Supply Voltage (Vcc, nom.)

Supply Current (Icc, typ.)

Vdc

All specifications are typical unless otherwise noted and subject to change without notice.

APPLICATION NOTES

• AN-107 : How to Solder Z-COMM VCOs / PLLs

• AN-200 : Mounting and Grounding of Z-COMM PLLs

• AN-201 : PLL Fundamentals

AN-202 : PLL Functional Description

NOTES:

Reference Oscillator Signal: 5 MHz<f_osc<40 MHz

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