5秒后页面跳转
PLL1708DBQR PDF预览

PLL1708DBQR

更新时间: 2024-09-20 22:24:31
品牌 Logo 应用领域
BB /
页数 文件大小 规格书
22页 171K
描述
3.3 V DUAL PLL MULTICLOCK GENERATOR

PLL1708DBQR 数据手册

 浏览型号PLL1708DBQR的Datasheet PDF文件第2页浏览型号PLL1708DBQR的Datasheet PDF文件第3页浏览型号PLL1708DBQR的Datasheet PDF文件第4页浏览型号PLL1708DBQR的Datasheet PDF文件第5页浏览型号PLL1708DBQR的Datasheet PDF文件第6页浏览型号PLL1708DBQR的Datasheet PDF文件第7页 
ꢀ ꢁꢁꢂ ꢃꢄ ꢃ  
ꢀ ꢁꢁꢂ ꢃꢄ ꢅ  
SLES065 – DECEMBER 2002  
FEATURES  
APPLICATIONS  
D
27-MHz Master Clock Input  
D
D
D
D
D
D
D
HDD + DVD Recorders  
DVD Recorders  
HDD Recorders  
DVD Players  
D
Generated Audio System Clock (PLL1707):  
– SCKO0: 768 f (f = 44.1 kHz)  
S
S
– SCKO1: 768 f , 512 f (f = 48 kHz)  
S
S
S
– SCKO2: 256 f (f = 32, 44.1, 48, 64, 88.2,  
S
S
96 kHz)  
– SCKO3: 384 f (f = 32, 44.1, 48, 64, 88.2,  
S
S
DVD Add-On Cards for Multimedia PCs  
Digital HDTV Systems  
96 kHz)  
Generated Audio System Clock (PLL1708):  
– SCKO0: 768 f (f = 44.1 kHz)  
D
S
S
Set-Top Boxes  
– SCKO1: 768 f , 512 f , 384 f , 256 f  
S
S
S
S
(f = 48 kHz)  
S
– SCKO2: 256 f (f = 16, 22.05, 24, 32, 44.1,  
S
S
DESCRIPTION  
48, 64, 88.2, 96 kHz)  
– SCKO3: 384 f (f = 16, 22.05, 24, 32, 44.1,  
S
S
The PLL1707 and PLL1708 are low cost, phase-locked  
loop (PLL) multiclock generators. The PLL1707 and  
PLL1708 can generate four system clocks from a 27-MHz  
reference input frequency. The clock outputs of the  
PLL1707 can be controlled by sampling frequency-control  
pins and those of the PLL1708 can be controlled through  
serial-mode control pins. The device gives customers both  
cost and space savings by eliminating external  
components and enables customers to achieve the very  
low-jitter performance needed for high performance audio  
DACs and/or ADCs. The PLL1707 and PLL1708 are ideal  
for MPEG-2 applications which use a 27-MHz master  
clock such as DVD recorders, HDD recorders, DVD  
add-on cards for multimedia PCs, digital HDTV systems,  
and set-top boxes.  
48, 64, 88.2, 96 kHz)  
D
D
D
D
Zero PPM Error Output Clocks  
Low Clock Jitter: 50 ps (Typical)  
Multiple Sampling Frequencies (PLL1707):  
– f = 32, 44.1, 48, 64, 88.2, 96 kHz  
S
Multiple Sampling Frequencies (PLL1708):  
– f = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2,  
S
96 kHz  
D
D
D
3.3-V Single Power Supply  
PLL1707: Parallel Control  
PLL1708: Serial Control  
Package: 20-Pin SSOP (150 mil), Lead-Free  
Product  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate  
precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to  
damage because very small parametric changes could cause the device not to meet its published specifications.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
The PLL1707 and PLL1708 use the same die and they are electrically identical except for mode control.  
ꢀꢖ ꢑ ꢊꢋ ꢐ ꢎꢏ ꢑꢕ ꢊ ꢌꢎꢌ ꢗꢘ ꢙꢚ ꢛ ꢜꢝ ꢞꢗꢚꢘ ꢗꢟ ꢠꢡ ꢛ ꢛ ꢢꢘꢞ ꢝꢟ ꢚꢙ ꢣꢡꢤ ꢥꢗꢠ ꢝꢞꢗ ꢚꢘ ꢦꢝ ꢞꢢꢇ ꢀꢛ ꢚꢦꢡ ꢠꢞꢟ  
ꢠ ꢚꢘ ꢙꢚꢛ ꢜ ꢞꢚ ꢟ ꢣꢢ ꢠ ꢗ ꢙꢗ ꢠ ꢝ ꢞꢗ ꢚꢘꢟ ꢣ ꢢꢛ ꢞꢧꢢ ꢞꢢ ꢛ ꢜꢟ ꢚꢙ ꢎꢢꢨ ꢝꢟ ꢏꢘꢟ ꢞꢛ ꢡꢜ ꢢꢘꢞ ꢟ ꢟꢞ ꢝꢘꢦ ꢝꢛ ꢦ ꢩ ꢝꢛ ꢛ ꢝ ꢘꢞꢪꢇ  
ꢀꢛ ꢚ ꢦꢡꢠ ꢞ ꢗꢚ ꢘ ꢣꢛ ꢚ ꢠ ꢢ ꢟ ꢟ ꢗꢘ ꢫ ꢦꢚ ꢢ ꢟ ꢘꢚꢞ ꢘꢢ ꢠꢢ ꢟꢟ ꢝꢛ ꢗꢥ ꢪ ꢗꢘꢠ ꢥꢡꢦ ꢢ ꢞꢢ ꢟꢞꢗ ꢘꢫ ꢚꢙ ꢝꢥ ꢥ ꢣꢝ ꢛ ꢝꢜ ꢢꢞꢢ ꢛ ꢟꢇ  
Copyright 2002, Texas Instruments Incorporated  

与PLL1708DBQR相关器件

型号 品牌 获取价格 描述 数据表
PLL1708DBQRG4 TI

获取价格

4.096MHz 至 36.864MHz、串行控制、3.3V 双路 PLL 多时钟发生器
PLL1720A ETC

获取价格

PHASE LOCKED LOOP
PLL1810A ETC

获取价格

PHASE LOCKED LOOP
PLL2_C0 ALTERA

获取价格

Cyclone III Device Handbook
PLL2_C1 ALTERA

获取价格

Cyclone III Device Handbook
PLL2_C2 ALTERA

获取价格

Cyclone III Device Handbook
PLL2_C3 ALTERA

获取价格

Cyclone III Device Handbook
PLL2_C4 ALTERA

获取价格

Cyclone III Device Handbook
PLL200 NPC

获取价格

SERIAL INPUT PLL FREQUENCY SYNTHESIZER
PLL2001014 ETC

获取价格

Analog IC