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PI74AVCH16373AX PDF预览

PI74AVCH16373AX

更新时间： 2024-09-16 15:47:55
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
5页 342K
描述
Bus Driver, AVC Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.240 INCH, PLASTIC, TSSOP-48

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中文翻译

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PI74AVCH16373AX 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.36
系列：AVCJESD-30 代码：R-PDSO-G48
JESD-609代码：e0长度：12.5 mm
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：5.9 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
宽度：6.1 mmBase Number Matches：1

PI74AVCH16373AX 数据手册

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ADVANCE INFORMATION  
PI74AVC16373  
PI74AVCH16373  
16-Bit Transparent D-Type Latch  
with 3-State Outputs  
Product Features  
ProductDescription  
Pericom Semiconductor’s PI74AVC series of logic circuits are  
produced using the Company’s advanced 0.35 micron CMOS  
technology, achieving industry leading speed.  
• Designed for low voltage operation,  
V
CC  
from 1.65V to 3.6V  
• Sub 2.0ns delays at 2.5V and 3.3V  
The 16-bit transparent D-type latch is designed for implementing  
buffer registers, I/O ports, bidirectional bus drivers, and working  
registers. This device can be used as two 8-bit latches or one 16-bit  
latch. When the Latch Enable (LE) input is HIGH, the Q outputs  
follow the (D) inputs. When LE is taken LOW, the Q outputs are  
latched at the levels set up at the D inputs.  
• Dynamic Impedance Control on outputs,  
current drive > ±24mA at 2.5V V  
CC  
• Patented noise reduction circuit  
• I/O Tolerant to 3.6V, Inputs and Outputs  
for mixed voltage systems  
• Supports live insertion  
A buffered Output Enable (OE) input can be used to place the  
eight outputs in either a normal logic state (high or low logic  
levels) or a high-impedance state in which the outputs neither  
loadnordrivethebuslinessignificantly.Thehigh-impedancestate  
and the increased drive provide the capability to drive bus lines  
without need for interface or pullup components. OE does not  
affect internal operations of the latch. Old data can be retained  
or new data can be entered while the outputs are in the high  
impedance state.  
• Industrial operation at –40°C to +85°C  
• Available Packages:  
– 48-pin 240 mil wide plastic TSSOP (A48)  
– 48-pin 173 mil wide plastic TVSOP (K48)  
Logic Block Diagram  
To ensure the high impedance state during power up or power  
1
down, OE should be tied to V through a pullup resistor; the  
CC  
1OE  
minimumvalue of the resistor is determined by the current-sinking  
capability of the driver.  
48  
1LE  
The PI74AVCH16373 has “Bus Hold” which retains the data  
input’s last state whenever the data input goes to high-  
impedance preventing “floating” inputs and eliminating the need  
for pullup/down resistors.  
C1  
2
1Q1  
47  
1D1  
1D  
To Seven Other Channels  
24  
25  
2OE  
2LE  
C1  
1D  
13  
2Q1  
36  
2D1  
To Seven Other Channels  
PXXXX  
02/02/99  
1
12345

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 		Bus Driver, AVC Series, 2-Func, 10-Bit, True Output, CMOS, PDSO48, 0.173 INCH, PLASTIC, TV
PI74AVCH16821KX PERICOM

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 		Bus Driver, AVC Series, 2-Func, 10-Bit, True Output, CMOS, PDSO48, 0.173 INCH, PLASTIC, TV
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 		Bus Driver, AVC Series, 2-Func, 10-Bit, True Output, CMOS, PDSO48, 0.240 INCH, PLASTIC, TS

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