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PI74AVCH16374K PDF预览

PI74AVCH16374K

更新时间： 2024-11-06 15:47:55
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路触发器电视
页数 文件大小 规格书
5页 343K
描述
Bus Driver, AVC Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.173 INCH, PLASTIC, TVSOP-48

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中文翻译

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PI74AVCH16374K 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：TSSOP, TSSOP48,.25,16
针数：48Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.76系列：AVC
JESD-30 代码：R-PDSO-G48JESD-609代码：e0
长度：9.7 mm逻辑集成电路类型：BUS DRIVER
最大频率@ Nom-Sup：150000000 Hz最大I（ol）：0.024 A
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.25,16封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 VProp。Delay @ Nom-Sup：4.2 ns
传播延迟（tpd）：5.3 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.4 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：4.4 mmBase Number Matches：1

PI74AVCH16374K 数据手册

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ADVANCE INFORMATION  
PI74AVC16374  
PI74AVCH16374  
16-Bit Edge Triggered D-Type Flip-Flop  
with 3-State Outputs  
Product Features  
ProductDescription  
Pericom Semiconductor’s PI74AVC series of logic circuits are  
produced in the Company’s advanced 0.35 micron CMOS  
technology, achieving industry leading speed.  
• Designed for low voltage operation,  
V
CC  
from 1.65V to 3.6V  
• Sub 2.0ns delays at 2.5V and 3.3V  
The 16-bit edge-triggered D-type flip-flop is designed for  
implementing buffer registers, I/O ports, bidirectional bus drivers,  
andworkingregisters.Thisdevicecanbeusedastwo8-bitflip-flops  
orone16-bitflip-flop.OnthepositivetransitionoftheClock(CLK)  
input, the Q outputs of the flip-flop take on the logic levels set up  
at the data (D) inputs. OE can be used to place the eight outputs in  
either a normal logic state (high or low logic levels) or a high-  
impedance state. In that state, the outputs neither load nor drive the  
buslinessignificantly. Thehigh-impedancestateandtheincreased  
drive provide the capability to drive bus lines without need for  
interface or pullup components. OE does not affect internal  
operationsoftheflip-flop. Olddatacanberetainedornewdatacan  
be entered while the outputs are in the high-impedance state.  
• Dynamic Impedance Control on outputs,  
current drive > ±24mA at 2.5V V  
CC  
• Patented noise reduction circuit  
• I/O Tolerant to 3.6V, Inputs and Outputs  
for mixed voltage systems  
• Supports live insertion  
• Industrial operation at –40°C to +85°C  
• Available Packages:  
– 48-pin 240 mil wide plastic TSSOP (A48)  
– 48-pin 173 mil wide plastic TVSOP (K48)  
To ensure the high-impedance state during power up or power  
LogicBlockDiagram  
down, OE should be tied to V through a pullup resistor; the  
CC  
minimumvalue of the resistor is determined by the current-sinking  
capability of the driver.  
1
1OE  
The PI74AVCH16374 has “Bus Hold” which retains the data  
input’s last state whenever the data input goes to high-  
impedance preventing “floating” inputs and eliminating the need  
for pullup/down resistors.  
48  
1CLK  
C1  
2
1Q1  
47  
1D1  
1D  
To Seven Other Channels  
24  
25  
2OE  
2CLK  
C1  
1D  
13  
2Q1  
36  
2D1  
To Seven Other Channels  
PSXXXX 02/02/99  
1
12345

中文翻译

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