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PI74ALVTC16823KX PDF预览

PI74ALVTC16823KX

更新时间: 2024-10-28 14:44:11
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路电视
页数 文件大小 规格书
8页 133K
描述
Bus Driver, ALVT Series, 2-Func, 9-Bit, True Output, CMOS, PDSO56, 0.173 INCH, PLASTIC, TVSOP-56

PI74ALVTC16823KX 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:TSSOP,针数:56
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N系列:ALVT
JESD-30 代码:R-PDSO-G56JESD-609代码:e0
长度:11.3 mm逻辑集成电路类型:BUS DRIVER
位数:9功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):4.9 ns认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.4 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

PI74ALVTC16823KX 数据手册

 浏览型号PI74ALVTC16823KX的Datasheet PDF文件第2页浏览型号PI74ALVTC16823KX的Datasheet PDF文件第3页浏览型号PI74ALVTC16823KX的Datasheet PDF文件第4页浏览型号PI74ALVTC16823KX的Datasheet PDF文件第5页浏览型号PI74ALVTC16823KX的Datasheet PDF文件第6页浏览型号PI74ALVTC16823KX的Datasheet PDF文件第7页 
PI74ALVTC16823  
2.5V 18-Bit Bus Interface  
Flip-Flop with 3-State Outputs  
ProductDescription  
ProductFeatures  
Pericom Semiconductor’s PI74ALVTC series of logic circuits are  
produced using the Company’s advanced 0.35 micron CMOS  
technology, achieving industry leading speed.  
• PI74ALVTC16823isdesignedforlowvoltageoperation,  
V
DD  
=1.65Vto3.6V  
• Supports Live Insertion  
ThePI74ALVTC16823 18-bitbus-interfaceflip-flopisdesignedfor  
• 3.6V I/O Tolerant Inputs and Outputs  
• Bus Hold  
1.65V to 3.6V V operation. It features 3-state outputs designed  
CC  
specificallyfordrivinghighlycapacitiveorrelativelylow-impedance  
loads. This device is particularly suitable for implementing wider  
bufferregisters,I/Oports,bidirectionalbusdriverswithparity,and  
workingregisters.  
• HighDrive,–32/64mA@3.3V  
• Uses patented noise reduction circuitry  
• Power-off high impedance inputs and outputs  
• Industrial operation at –40°C to +85°C  
• Packagesavailable:  
Thedevicecanbeusedastwo9-bitflip-flopsorone18-bitflip-flop.  
WiththeClockEnable(CLKEN)inputLOW, theD-typeflip-flops  
enter data on the low-to-high transitions of the clock. Taking  
CLKEN HIGH disables the clock buffer, thus latching the outputs.  
TakingtheClear(CLR)inputLOWcausestheQoutputstogoLOW  
independently of the clock.  
–56-pin240-milwideplasticTSSOP(A56)  
–56-pin173-milwideplasticTVSOP(K56)  
A buffered Output Enable (OE) input can be used to place the nine  
outputs in either a normal logic state (high or low logic levels) or  
high-impedance state. In the high-impedance state, the outputs  
neither load n or drive the bus lines significantly. The high-  
impedance state and increased drive provide the capability to drive  
bus lines without need for interface or pullup components.  
Logic Block Diagram  
2
1OE  
1
1CLR  
Toensurethehigh-impedancestateduringpoweruporpowerdown,  
OE should be tied to V through a pullup resistor; the minimum  
value of the resistor is determined by the current-sinking capability  
of the driver.  
55  
DD  
CE  
R
1
CLKEN  
56  
54  
3
C1  
1CLK  
1Q1  
1D1  
The family offers both I/O Tolerant, which allows it to operate in  
mixed 1.65/3.6V systems, and “Bus Hold,” which retains the data  
input’s last state preventing “floating” inputs and eliminating the  
need for pullup/down resistors.  
1D  
TO 8 OTHER CHANNELS  
27  
2OE  
28  
30  
2
CLR  
2
CLKEN  
CE  
R
C1  
15  
29  
42  
2CLK  
2Q1  
2D1  
1D  
TO 8 OTHER CHANNELS  
PS8620  
06/05/02  
1

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