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PI74AVC+16244AX PDF预览

PI74AVC+16244AX

更新时间: 2024-10-28 14:35:15
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
11页 425K
描述
Bus Driver, AVC Series, 4-Func, 4-Bit, True Output, CMOS, PDSO48, 0.240 INCH, PLASTIC, TSSOP-48

PI74AVC+16244AX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP48,.3,20
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.27控制类型:ENABLE LOW
系列:AVCJESD-30 代码:R-PDSO-G48
长度:12.5 mm负载电容(CL):30 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
位数:4功能数量:4
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:1.7 ns传播延迟(tpd):3.3 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.4 V标称供电电压 (Vsup):1.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.1 mm
Base Number Matches:1

PI74AVC+16244AX 数据手册

 浏览型号PI74AVC+16244AX的Datasheet PDF文件第2页浏览型号PI74AVC+16244AX的Datasheet PDF文件第3页浏览型号PI74AVC+16244AX的Datasheet PDF文件第4页浏览型号PI74AVC+16244AX的Datasheet PDF文件第5页浏览型号PI74AVC+16244AX的Datasheet PDF文件第6页浏览型号PI74AVC+16244AX的Datasheet PDF文件第7页 
PI74AVC+16244  
2.5V 16-Bit Buffer Driver  
with 3-State Outputs  
Product Features  
ProductDescription  
• PI74AVC+16244 is designed for low-voltage operation,  
VCC = 1.65V to 3.6V  
PI74AVC+16244 is a non-inverting 16-bit buffer/driver designed  
forlow-voltage1.65Vto3.6VV operation.  
CC  
• True ±24mA Balanced Drive @ 3.3V  
The buffer/driver is designed specifically to improve both the  
performance and density of 3-state memory address drivers, clock  
drivers, and bus-oriented receivers and transmitters.  
• Compatible with Philips and T.I.AVC Logic family  
• IOFF supports partial power-down operation  
• 3.6V I/O Tolerant inputs and outputs  
The device can be used as four 4-bit buffers, two 8-bit buffers, or  
one 16-bit buffer. It provides non-inverting outputs and symmetri-  
cal active-low output-enable (OE) inputs.  
• All outputs contain a patented DDC  
(Dynamic Drive Control) circuit that reduces noise without  
degrading propagation delay  
To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pullup resistor in which  
the minimum value is determined by the current-sinking capability  
of the driver.  
• Industrial operation: –40°C to +85°C  
• Packaging (Pb-free & Green available):  
– 48-pin 240-mil wide plastic TSSOP  
– 48-pin 173-mil wide plastic TVSOP  
LogicBlockDiagram  
1
25  
1OE  
3OE  
47  
46  
2
3
36  
35  
13  
14  
1A1  
1A2  
1A3  
1A4  
1Y1  
1Y2  
1Y3  
1Y4  
3A1  
3A2  
3A3  
3A4  
3Y1  
3Y2  
3Y3  
3Y4  
44  
43  
5
6
33  
32  
16  
17  
24  
30  
48  
41  
2OE  
2A1  
4OE  
4A1  
19  
20  
8
9
2Y1  
2Y2  
2Y3  
2Y4  
4Y1  
4Y2  
4Y3  
4Y4  
29  
27  
26  
40  
38  
37  
2A2  
2A3  
2A4  
4A2  
4A3  
4A4  
22  
23  
11  
12  
PS8507B  
05/31/06  
1
06-0164  

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