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PI74AVC+16345K PDF预览

PI74AVC+16345K

更新时间: 2024-10-27 22:34:43
品牌 Logo 应用领域
百利通 - PERICOM 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
10页 475K
描述
2.5V, Registered 1-Bit to 4-Bit Address Driver w/3-State Outputs

PI74AVC+16345K 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:TSSOP, TSSOP56,.25,16
针数:56Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92Is Samacsys:N
其他特性:QUAD OUTPUTS系列:AVC
JESD-30 代码:R-PDSO-G56JESD-609代码:e0
长度:11.3 mm逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:5端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.25,16封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V传播延迟(tpd):4.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Other Logic ICs最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.4 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

PI74AVC+16345K 数据手册

 浏览型号PI74AVC+16345K的Datasheet PDF文件第2页浏览型号PI74AVC+16345K的Datasheet PDF文件第3页浏览型号PI74AVC+16345K的Datasheet PDF文件第4页浏览型号PI74AVC+16345K的Datasheet PDF文件第5页浏览型号PI74AVC+16345K的Datasheet PDF文件第6页浏览型号PI74AVC+16345K的Datasheet PDF文件第7页 
PI74AVC+16345  
2.5V, Registered 1-Bit to 4-Bit Address  
Driver w/3-State Outputs  
ProductDescription  
Product Features  
Pericom Semiconductor’s PI74AVC+ series of logic circuits are  
produced using the Company’s advanced submicron CMOS  
technology, achieving industry leading speed.  
• PI74AVC+16345 is designed for low-voltage operation,  
V
CC  
= 1.65V to 3.6V  
• True ±24mA Balanced Drive @3.3V  
• I supports partial power down operation  
The PI74AVC+16345 is ideal for driving memory modules in  
systemswheremultiplememorymodulesareused. Oneeachofthe  
four output banks drive a different module; modules can be added  
or removed without affecting the signal integrity of the other  
modules in the system. Dual clock enables (CEx) allow use of the  
device in high-speed memory interleaving applications where the  
clockcanbealternatelyenabledanddisabled, allowingtheaddress  
to be held for additional cycles during memory access.  
OFF  
• I/O Tolerant to 3.6V  
• All outputs contain a patented DDC  
(Dynamic DriveControl) circuit that reduces noise without  
degrading propagation delay.  
• Industrial operation: –40°C to +85°C  
• Available Packages:  
To ensure the high-impedance state during power up or power  
– 56-pin 240 mil wide plastic TSSOP (A)  
– 56-pin 173 mil wide plastic TVSOP (K)  
down, OE should be tied to V through a pullup resistor; the  
CC  
minimum value of the resistor is determined by the current sinking  
capability of the driver.  
LogicBlockDiagram  
1
56  
CE1  
CE2  
29  
OE  
1Q1  
1Q5  
CE  
CE  
8
36  
D1  
D2  
D5  
D6  
D
D
D
D
4Q1  
1Q2  
4Q2  
1Q3  
4Q5  
1Q6  
4Q6  
1Q7  
CE  
CE  
14  
42  
CE  
CE  
CE  
CE  
15  
43  
D3  
D
D
D7  
D8  
D
D
4Q3  
1Q4  
4Q4  
4Q7  
1Q8  
4Q8  
21  
28  
49  
D4  
CLK  
PS8442A  
08/06/01  
1

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