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PI74AVC+16268A PDF预览

PI74AVC+16268A

更新时间: 2024-10-27 23:27:39
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其他 - ETC /
页数 文件大小 规格书
11页 514K
描述
Bus Exchanger

PI74AVC+16268A 数据手册

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PI74AVC+16268  
12-Bit to 24-Bit Registered Bus  
Exchanger with 3-State Outputs  
ProductDescription  
Product Features  
Pericom Semiconductor’s PI74AVC+ series of logic circuits are  
produced using the Company’s advanced submicron CMOS  
technology, achieving industry leading speed.  
• PI74AVC+16268 is designed for low-voltage operation,  
V
= 1.65V to 3.6V  
CC  
• True ±24mA Balanced Drive @ 3.3V  
• I supports partial power-down operation  
The PI74AVC+16268, a 12-bit to 24-bit registered bus exchanger  
OFF  
designedfor1.65Vto3.6VV operation, isusedforapplications  
CC  
• 3.6 I/O Tolerant Inputs and Outputs  
in which data must be transferred from a narrow high-speed bus to  
awide,lowerfrequencybus.Itprovidessynchronousdataexchange  
betweenthetwoports.Dataisstoredininternalregistersonthelow-  
to-hightransitionof theclock(CLK)inputwhenappropriateclock-  
enable(CLKEN)inputsarelow.Theselect(SEL)lineissynchronous  
with CLK and selects 1B or 2B input data for the A outputs.  
• All outputs contain a patented DDC  
(Dynamic DriveControl) circuit that reduces noise without  
degrading propagation delay.  
• Industrial operation: –40°C to +85°C  
• Available Packages:  
For data transfer in the A-to-B direction, a two-stage pipeline is  
provided in the A-to-1B path, with a single storage register in the  
A-to-2B path. Proper control of these inputs allows two sequential  
12-bit words to be presented synchronously as a 24-bit word on the  
B-port. Data flow is controlled by the active-low output enables  
(OEA,OEB).Thesecontrolterminalsareregisteredsobusdirection  
changes are synchronous with CLK.  
– 56-pin 240 mil wide plastic TSSOP (A)  
– 56-pin 173 mil wide plastic TVSOP (K)  
To ensure the high-impedance state during power up or power  
down, a clock pulse should be applied as soon as possible and OE  
shouldbetiedtoV through a pullup resistor, the minimumvalue  
CC  
oftheresistorisdeterminedbythecurrent-sinkingcapabilityofthe  
driver. Because OE is being routed through a register, the active  
state of the outputs cannot be determined prior to the arrival of the  
first clock pulse.  
LogicBlockDiagram  
29  
CLK  
2
CLKEN1B  
27  
30  
CLKEN2B  
CLKENA1  
55  
56  
28  
1
CLKENA2  
OEB  
C1  
1D  
C1  
1D  
SEL  
OEA  
CE  
1D  
C1  
C1  
23  
1B1  
1D  
1D  
G1  
CE  
C1  
1
1
6
8
A1  
2B1  
CE  
CE  
C1  
C1  
1D  
1D  
CE  
C1  
1D  
1 of 12 Channels  
PS8551  
07/31/01  
1

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