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PI74ALVTC16841AX PDF预览

PI74ALVTC16841AX

更新时间： 2024-10-28 15:47:55
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 172K
描述
Bus Driver, ALVT Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.240 INCH, PLASTIC, TSSOP-56

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中文翻译

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PI74ALVTC16841AX 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP,
针数：56Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.92Is Samacsys：N
系列：ALVTJESD-30 代码：R-PDSO-G56
JESD-609代码：e0长度：14 mm
逻辑集成电路类型：BUS DRIVER湿度敏感等级：1
位数：10功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：240传播延迟（tpd）：5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：6.1 mm
Base Number Matches：1

PI74ALVTC16841AX 数据手册

 浏览型号PI74ALVTC16841AX的Datasheet PDF文件第2页浏览型号PI74ALVTC16841AX的Datasheet PDF文件第3页浏览型号PI74ALVTC16841AX的Datasheet PDF文件第4页浏览型号PI74ALVTC16841AX的Datasheet PDF文件第5页浏览型号PI74ALVTC16841AX的Datasheet PDF文件第6页浏览型号PI74ALVTC16841AX的Datasheet PDF文件第7页 
PI74ALVTC16841  
2.5V 20-Bit Bus Interface  
D-Type Latch with 3-State Outputs  
ProductDescription  
Pericom Semiconductor’s PI74ALVTC series of logic circuits are  
produced using the Company’s advanced 0.35 micron CMOS  
technology, achieving industry leading speed.  
ThePI74ALVTC16841features3-Stateoutputsdesignedspecifically  
fordrivinghighlycapacitiveorrelativelylow-impedenceloads.This  
device is particularly suitable for implementing buffer registers,  
unidirectional bus drivers, and working registers.  
Thedevicecanbeusedastwo10-bitlatches,orone20-bitlatch.The  
20 latches are transparent D-type latches. The device has non-  
invertingdata(D)inputsandprovidestruedataatitsoutputs. While  
the latch-enable (1LE or 2LE) input is high, the Q outputs of the  
corresponding 10-bit latch follows the D inputs. When LE is taken  
low, the Q outputs are latched at the levels set up at the D inputs.  
ProductFeatures  
• PI74ALVTC16841isdesignedforlowvoltageoperation,  
V
DD  
=1.65Vto3.6V  
• Supports Live Insertion  
• 3.6V I/O Tolerant Inputs and Outputs  
• Bus Hold  
• HighDrive,–32/64mA@3.3V  
• Uses patented noise reduction circuitry  
• Power-off high impedance inputs and outputs  
• Industrial operation at –40°C to +85°C  
• Packagesavailable:  
–56-pin240-milwideplasticTSSOP(A56)  
–56-pin173-milwideplasticTVSOP(K56)  
A buffered output-enable (1OE or 2OE) input can be used to place  
theoutputsofthecorresponding10-bitlatchineitheranormallogic  
state(highorlowlogiclevels)orahigh-impedencestate.Inthehigh-  
impedence state, the outputs neither load nor drive the bus lines  
significantly.  
Logic Block Diagram  
The output enable (OE) input does not affect the internal operation  
of the latches. Old data can be retained or new data or new data can  
be entered while the outputs are in the high-impedence state.  
1
1OE  
56  
1LE  
Toensurethehigh-impedancestateduringpoweruporpowerdown,  
OE should be tied to V through a pullup resistor; the minimum  
DD  
value of the resistor is determined by the current-sinking capability  
L
of the driver.  
2
1Q0  
Q
55  
The family offers both I/O Tolerant, which allows it to operate in  
mixed 1.65/3.6V systems, and “Bus Hold,” which retains the data  
input’s last state preventing “floating” inputs and eliminating the  
need for pullup/down resistors.  
1D0  
D
To Nine Other Channels  
28  
29  
2OE  
2LE  
L
15  
2Q0  
Q
D
42  
2D0  
To Nine Other Channels  
PS8643  
10/29/02  
1
12345678

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