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PI74ALVTC16841 PDF预览

PI74ALVTC16841

更新时间: 2024-10-27 23:27:39
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其他 - ETC 锁存器
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8页 236K
描述
Logic | 20-Bit Bus Interface D-Type Latch

PI74ALVTC16841 数据手册

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PI74ALVTC16841  
2.5V 20-Bit Bus Interface  
D-Type Latch with 3-State Outputs  
ProductDescription  
ProductFeatures  
Pericom Semiconductor’s PI74ALVTC series of logic circuits are  
produced using the Company’s advanced 0.35 micron CMOS  
technology, achieving industry leading speed.  
• PI74ALVTC16841isdesignedforlowvoltageoperation,  
V
DD  
=1.65Vto3.6V  
• Supports Live Insertion  
ThePI74ALVTC16841features3-Stateoutputsdesignedspecifically  
fordrivinghighlycapacitiveorrelativelylow-impedenceloads.This  
device is particularly suitable for implementing buffer registers,  
unidirectional bus drivers, and working registers.  
• 3.6V I/O Tolerant Inputs and Outputs  
• Bus Hold  
• HighDrive,–32/64mA@3.3V  
• Uses patented noise reduction circuitry  
• Power-off high impedance inputs and outputs  
• Industrial operation at –40°C to +85°C  
• Packagesavailable:  
Thedevicecanbeusedastwo10-bitlatches,orone20-bitlatch.The  
20 latches are transparent D-type latches. The device has non-  
invertingdata(D)inputsandprovidestruedataatitsoutputs. While  
the latch-enable (1LE or 2LE) input is high, the Q outputs of the  
corresponding 10-bit latch follows the D inputs. When LE is taken  
low, the Q outputs are latched at the levels set up at the D inputs.  
–56-pin240-milwideplasticTSSOP(A56)  
–56-pin173-milwideplasticTVSOP(K56)  
A buffered output-enable (1OE or 2OE) input can be used to place  
theoutputsofthecorresponding10-bitlatchineitheranormallogic  
state(highorlowlogiclevels)orahigh-impedencestate.Inthehigh-  
impedence state, the outputs neither load nor drive the bus lines  
significantly.  
Logic Block Diagram  
The output enable (OE) input does not affect the internal operation  
of the latches. Old data can be retained or new data or new data can  
be entered while the outputs are in the high-impedence state.  
1
1OE  
56  
1LE  
Toensurethehigh-impedancestateduringpoweruporpowerdown,  
OE should be tied to V through a pullup resistor; the minimum  
DD  
value of the resistor is determined by the current-sinking capability  
of the driver.  
L
2
1Q0  
Q
55  
The family offers both I/O Tolerant, which allows it to operate in  
mixed 1.65/3.6V systems, and “Bus Hold,” which retains the data  
input’s last state preventing “floating” inputs and eliminating the  
need for pullup/down resistors.  
1D0  
D
To Nine Other Channels  
28  
29  
2OE  
2LE  
L
15  
2Q0  
Q
D
42  
2D0  
To Nine Other Channels  
P0.2  
04/09/02  
1

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