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PI74ALVTC16821 PDF预览

PI74ALVTC16821

更新时间: 2024-10-27 23:27:39
品牌 Logo 应用领域
其他 - ETC 触发器
页数 文件大小 规格书
9页 141K
描述
Logic | 20-Bit Bus Interface Flip-Flop

PI74ALVTC16821 数据手册

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PI74ALVTC16821  
2.5V 20-Bit Bus Interface  
Flip-Flop with 3-State Outputs  
Product Features  
Description  
• PI74ALVTC16821isdesignedforlowvoltageoperation,  
Pericom Semiconductor’s PI74ALVTC series of logic circuits are  
produced using the Company’s advanced 0.35 micron CMOS  
technology, achieving industry leading speed.  
V
DD  
=1.65Vto3.6V  
• Supports Live Insertion  
• 3.6V I/O Tolerant Inputs and Outputs  
• Bus Hold  
ThePI74ALVTC16821isa20-bit businterfaceflip-flopdesignedfor  
1.65V to3.6V VCC operation. Itcanbeusedastwo10-bitflip-flops  
or one 20-bit flip-flop. The 20 flip-flops are edge-triggered D-type  
flip-flops. On the positive transition of the clock (CLK) input, the  
device provides true data at the Q outputs.  
• HighDrive,–32/64mA@3.3V  
• Uses patented noise reduction circuitry  
• Power-off high impedance inputs and outputs  
• Industrial operation at –40°C to +85°C  
• Packagesavailable:  
A buffered output-enable (OE) input can be used to place the ten  
outputsineitheranormallogicstate(HIGHorLOWlevel)orahigh-  
impedance state. In the high-impedance state, the outputs neither  
loadnordrivethebuslinessignificantly. Thehigh-impedancestate  
and increased drive provide the capacity to drive bus lines without  
the need for interface or pullup components.  
–56-pin240-milwideplasticTSSOP(A56)  
–56-pin173-milwideplasticTVSOP(K56)  
OE does not affect the internal operation of the flip-flops. Old data  
can be retained or new data can be entered while the outputs are in  
the high-impedance state.  
To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pullup resistor; the  
minimum value of the resistor is determined by the current sinking  
capability of the driver.  
The family offers both I/O Tolerant, which allows it to operate in  
mixed 1.65/3.6V systems, and “Bus Hold,” which retains the data  
input’s last state preventing “floating” inputs and eliminating the  
need for pullup/down resistors.  
Logic Block Diagram  
1
28  
1OE  
2OE  
56  
55  
29  
42  
1CLK  
2CLK  
One of Ten  
Channels  
One of Ten  
Channels  
C
1
C1  
2
15  
1D1  
1Q  
1
2D1  
2Q1  
1
D
1D  
TO 9 OTHER CHANNELS  
TO 9 OTHER CHANNELS  
PS8618  
06/05/02  
1

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