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PI74ALVTC16821K PDF预览

PI74ALVTC16821K

更新时间: 2024-10-28 15:47:55
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路触发器电视
页数 文件大小 规格书
9页 137K
描述
Bus Driver, ALVT Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.173 INCH, PLASTIC, TVSOP-56

PI74ALVTC16821K 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:TSSOP, TSSOP56,.25,16
针数:56Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92系列:ALVT
JESD-30 代码:R-PDSO-G56JESD-609代码:e0
长度:11.3 mm负载电容(CL):30 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:180000000 Hz
最大I(ol):0.064 A位数:10
功能数量:2端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP56,.25,16
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:3.2 ns传播延迟(tpd):5.2 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.4 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:4.4 mm
Base Number Matches:1

PI74ALVTC16821K 数据手册

 浏览型号PI74ALVTC16821K的Datasheet PDF文件第2页浏览型号PI74ALVTC16821K的Datasheet PDF文件第3页浏览型号PI74ALVTC16821K的Datasheet PDF文件第4页浏览型号PI74ALVTC16821K的Datasheet PDF文件第5页浏览型号PI74ALVTC16821K的Datasheet PDF文件第6页浏览型号PI74ALVTC16821K的Datasheet PDF文件第7页 
PI74ALVTC16821  
2.5V 20-Bit Bus Interface  
Flip-Flop with 3-State Outputs  
Product Features  
Description  
• PI74ALVTC16821isdesignedforlowvoltageoperation,  
Pericom Semiconductor’s PI74ALVTC series of logic circuits are  
produced using the Company’s advanced 0.35 micron CMOS  
technology, achieving industry leading speed.  
V
DD  
=1.65Vto3.6V  
• Supports Live Insertion  
• 3.6V I/O Tolerant Inputs and Outputs  
• Bus Hold  
ThePI74ALVTC16821isa20-bit businterfaceflip-flopdesignedfor  
1.65V to3.6V VCC operation. Itcanbeusedastwo10-bitflip-flops  
or one 20-bit flip-flop. The 20 flip-flops are edge-triggered D-type  
flip-flops. On the positive transition of the clock (CLK) input, the  
device provides true data at the Q outputs.  
• HighDrive,–32/64mA@3.3V  
• Uses patented noise reduction circuitry  
• Power-off high impedance inputs and outputs  
• Industrial operation at –40°C to +85°C  
• Packagesavailable:  
A buffered output-enable (OE) input can be used to place the ten  
outputsineitheranormallogicstate(HIGHorLOWlevel)orahigh-  
impedance state. In the high-impedance state, the outputs neither  
loadnordrivethebuslinessignificantly. Thehigh-impedancestate  
and increased drive provide the capacity to drive bus lines without  
the need for interface or pullup components.  
–56-pin240-milwideplasticTSSOP(A56)  
–56-pin173-milwideplasticTVSOP(K56)  
OE does not affect the internal operation of the flip-flops. Old data  
can be retained or new data can be entered while the outputs are in  
the high-impedance state.  
To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pullup resistor; the  
minimum value of the resistor is determined by the current sinking  
capability of the driver.  
The family offers both I/O Tolerant, which allows it to operate in  
mixed 1.65/3.6V systems, and “Bus Hold,” which retains the data  
input’s last state preventing “floating” inputs and eliminating the  
need for pullup/down resistors.  
Logic Block Diagram  
1
28  
1OE  
2OE  
56  
55  
29  
42  
1CLK  
2CLK  
One of Ten  
Channels  
One of Ten  
Channels  
C
1
C1  
2
15  
1D1  
1Q  
1
2D1  
2Q1  
1
D
1D  
TO 9 OTHER CHANNELS  
TO 9 OTHER CHANNELS  
PS8618  
06/05/02  
1

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