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PI74ALVTC16721K PDF预览

PI74ALVTC16721K

更新时间: 2024-10-28 20:02:31
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路触发器电视
页数 文件大小 规格书
8页 139K
描述
Bus Driver, ALVT Series, 1-Func, 20-Bit, True Output, CMOS, PDSO56, 0.173 INCH, PLASTIC, TVSOP-56

PI74ALVTC16721K 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:TSSOP, TSSOP56,.25,16
针数:56Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92系列:ALVT
JESD-30 代码:R-PDSO-G56JESD-609代码:e0
长度:11.3 mm负载电容(CL):30 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:180000000 Hz
最大I(ol):0.064 A位数:20
功能数量:1端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP56,.25,16
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3.3 VProp。Delay @ Nom-Sup:3.3 ns
传播延迟(tpd):5 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.4 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:4.4 mm
Base Number Matches:1

PI74ALVTC16721K 数据手册

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PI74ALVTC16721  
2.5V 20-Bit Flip-Flop  
with 3-State Outputs  
ProductDescription  
ProductFeatures  
Pericom Semiconductor’s PI74ALVTC series of logic circuits are  
produced using the Company’s advanced 0.35 micron CMOS  
technology, achieving industry leading speed.  
• PI74ALVTC16721isdesignedforlowvoltageoperation,  
V
DD  
=1.65Vto3.6V  
• Supports Live Insertion  
The PI74ALVTC16721 is a 20-bit flip-flop with 3-state outputs  
• 3.6V I/O Tolerant Inputs and Outputs  
• Bus Hold  
designedspecificallyfor1.65Vto3.6VV operation.Thedevice  
DD  
is designed with edge-triggered D-type flip-flops with qualified  
clock storage. On the positive transition of clock (CLK) input, the  
device provides true data at the Q outputs, provided that the clock-  
enable(CLKEN)inputisLOW.If CLKENisHIGH,nodataisstored.  
• HighDrive,–32/64mA@3.3V  
• Uses patented noise reduction circuitry  
• Power-off high impedance inputs and outputs  
• Industrial operation at –40°C to +85°C  
• Packagesavailable:  
A buffered output-enable (OE) input can be used to place the  
20 outputs in either a normal logic state (HIGH or LOW level) or a  
high-impedance state. In the high-impedance state, the outputs  
neitherloadnordrivethebuslinessignificantly.Thehigh-impedance  
state and increased drive provide the capacity to drive bus lines  
without the need for interface or pullup components. OE does not  
affect the internal operation of the flip-flops. Old data can be  
retainedor newdatacanbeenteredwhiletheoutputsareinthehigh-  
impedance state.  
–56-pin240-milwideplasticTSSOP(A56)  
–56-pin173-milwideplasticTVSOP(K56)  
To ensure the high-impedance state during power up or power  
down, OE should be tied to V  
through a pullup resistor; the  
DD  
minimum value of the resistor is determined by the current-sinking  
capability of the driver.  
The family offers both I/O Tolerant, which allows it to operate in  
mixed 1.65/3.6V systems, and "Bus Hold," which retains the data  
input’s last state preventing "floating" inputs and eliminating the  
need for pullup/down resistors.  
Logic Block Diagram  
1
56  
29  
2
55  
PS8617  
06/05/02  
1

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