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PHX3055L PDF预览

PHX3055L

更新时间: 2024-11-20 22:26:31
品牌 Logo 应用领域
恩智浦 - NXP 晶体晶体管功率场效应晶体管开关脉冲局域网
页数 文件大小 规格书
7页 58K
描述
PowerMOS transistor Logic level FET

PHX3055L 技术参数

生命周期:Obsolete包装说明:FLANGE MOUNT, R-PSFM-T3
针数:3Reach Compliance Code:unknown
ECCN代码:EAR99风险等级:5.83
Is Samacsys:N其他特性:LOGIC LEVEL COMPATIBLE
雪崩能效等级(Eas):25 mJ外壳连接:ISOLATED
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:60 V
最大漏极电流 (ID):9.4 A最大漏源导通电阻:0.18 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PSFM-T3
元件数量:1端子数量:3
工作模式:ENHANCEMENT MODE封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:FLANGE MOUNT
极性/信道类型:N-CHANNEL最大脉冲漏极电流 (IDM):26 A
认证状态:Not Qualified表面贴装:NO
端子形式:THROUGH-HOLE端子位置:SINGLE
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

PHX3055L 数据手册

 浏览型号PHX3055L的Datasheet PDF文件第2页浏览型号PHX3055L的Datasheet PDF文件第3页浏览型号PHX3055L的Datasheet PDF文件第4页浏览型号PHX3055L的Datasheet PDF文件第5页浏览型号PHX3055L的Datasheet PDF文件第6页浏览型号PHX3055L的Datasheet PDF文件第7页 
Philips Semiconductors  
Preliminary specification  
PowerMOS transistor  
Logic level FET  
PHX3055L  
GENERAL DESCRIPTION  
QUICK REFERENCE DATA  
N-channel enhancement mode logic  
level field-effect power transistor in a  
plastic full-pack envelope. The  
device features high avalanche  
energy capability, stable blocking  
voltage, fast switching and high  
thermalcycling performance withlow  
thermal resistance. Intended for use  
in Switched Mode Power Supplies  
(SMPS), motor control circuits and  
SYMBOL  
PARAMETER  
MAX.  
UNIT  
VDS  
ID  
Drain-source voltage  
Drain current (DC)  
Total power dissipation  
Drain-source on-state resistance  
60  
9.4  
28  
V
A
W
Ptot  
RDS(ON)  
0.18  
general  
purpose  
switching  
applications.  
PINNING - SOT186A  
PIN CONFIGURATION  
SYMBOL  
PIN  
1
DESCRIPTION  
d
case  
gate  
2
drain  
g
3
source  
case isolated  
1
2 3  
s
LIMITING VALUES  
Limiting values in accordance with the Absolute Maximum System (IEC 134)  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
ID  
Continuous drain current  
Ths = 25 ˚C; VGS = 10 V  
Ths = 100 ˚C; VGS = 10 V  
Ths = 25 ˚C  
-
-
-
-
-
-
-
9.4  
5.9  
A
A
IDM  
PD  
Pulsed drain current  
Total dissipation  
26  
A
Ths = 25 ˚C  
28  
W
W/K  
V
PD/Ths Linear derating factor  
Ths > 25 ˚C  
0.22  
± 15  
± 20  
VGS  
VGSM  
Gate-source voltage  
Non-repetitive gate source  
voltage  
Single pulse avalanche  
energy  
Peak avalanche current  
tp50µs  
V
EAS  
V
DD 50 V; starting Tj = 25˚C; RGS = 50 ;  
VGS = 10 V  
DD 50 V; starting Tj = 25˚C; RGS = 50 ;  
VGS = 10 V  
-
-
25  
6
mJ  
A
IAS  
V
Tj, Tstg  
Operating junction and  
storage temperature range  
- 55  
150  
˚C  
ISOLATION LIMITING VALUE & CHARACTERISTIC  
Ths = 25 ˚C unless otherwise specified  
SYMBOL PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
Visol  
Cisol  
R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal  
-
2500  
V
three terminals to external  
heatsink  
waveform;  
R.H. 65% ; clean and dustfree  
Capacitance from T2 to external f = 1 MHz  
heatsink  
-
10  
-
pF  
October 1997  
1
Rev 1.000  

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