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PHX5N50E PDF预览

PHX5N50E

更新时间: 2024-11-20 22:12:39
品牌 Logo 应用领域
恩智浦 - NXP 晶体晶体管
页数 文件大小 规格书
5页 26K
描述
PowerMOS transistor Isolated version of PHP8N50E

PHX5N50E 技术参数

生命周期:Obsolete零件包装代码:SFM
包装说明:FLANGE MOUNT, R-PSFM-T3针数:3
Reach Compliance Code:compliant风险等级:5.76
其他特性:AVALANCHE RATED雪崩能效等级(Eas):510 mJ
外壳连接:ISOLATED配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:500 V最大漏极电流 (Abs) (ID):4 A
最大漏极电流 (ID):4 A最大漏源导通电阻:0.8 Ω
FET 技术:METAL-OXIDE SEMICONDUCTOR最大反馈电容 (Crss):120 pF
JESD-30 代码:R-PSFM-T3JESD-609代码:e3
元件数量:1端子数量:3
工作模式:ENHANCEMENT MODE最高工作温度:150 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:FLANGE MOUNT极性/信道类型:N-CHANNEL
功耗环境最大值:30 W最大功率耗散 (Abs):30 W
最大脉冲漏极电流 (IDM):16 A认证状态:Not Qualified
子类别:FET General Purpose Power表面贴装:NO
端子面层:TIN端子形式:THROUGH-HOLE
端子位置:SINGLE晶体管应用:SWITCHING
晶体管元件材料:SILICON最大关闭时间(toff):340 ns
最大开启时间(吨):130 nsBase Number Matches:1

PHX5N50E 数据手册

 浏览型号PHX5N50E的Datasheet PDF文件第2页浏览型号PHX5N50E的Datasheet PDF文件第3页浏览型号PHX5N50E的Datasheet PDF文件第4页浏览型号PHX5N50E的Datasheet PDF文件第5页 
Philips Semiconductors  
Objective specification  
PowerMOS transistor  
Isolated version of PHP8N50E  
PHX5N50E  
GENERAL DESCRIPTION  
QUICK REFERENCE DATA  
N-channel enhancement mode  
field-effect power transistor in a full  
pack, plastic envelope featuring high  
avalanche energy capability, stable  
blocking voltage, fast switching and  
high thermal cycling performance  
withlowthermalresistance. Intended  
for use in Switched Mode Power  
Supplies (SMPS), motor control  
circuits and general purpose  
switching applications.  
SYMBOL  
PARAMETER  
MAX.  
UNIT  
VDS  
ID  
Drain-source voltage  
Drain current (DC)  
Total power dissipation  
Drain-source on-state resistance  
500  
4
30  
0.8  
V
A
W
Ptot  
RDS(ON)  
PINNING - SOT186A  
PIN CONFIGURATION  
SYMBOL  
PIN  
1
DESCRIPTION  
d
case  
gate  
2
drain  
g
3
source  
case isolated  
1
2 3  
s
LIMITING VALUES  
Limiting values in accordance with the Absolute Maximum System (IEC 134)  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
VDS  
VDGR  
±VGS  
ID  
Drain-source voltage  
-
-
-
-
-
-
500  
500  
30  
V
V
V
A
A
A
Drain-gate voltage  
Gate-source voltage  
Drain current (DC)  
RGS = 20 kΩ  
Ths = 25 ˚C  
Ths = 100 ˚C  
Ths = 25 ˚C  
4
2.5  
16  
IDM  
Drain current (pulse peak  
value)  
Source-drain diode current  
(DC)  
Source-drain diode current  
(pulse peak value)  
Total power dissipation  
Storage temperature  
Junction temperature  
IDR  
Ths = 25 ˚C  
Ths = 25 ˚C  
Ths = 25 ˚C  
-
-
4
A
A
IDRM  
16  
Ptot  
Tstg  
Tj  
-
-55  
-
30  
150  
150  
W
˚C  
˚C  
AVALANCHE LIMITING VALUE  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
WDSS  
Drain-source non-repetitive ID = 8 A; VDD 50 V; VGS = 10 V;  
unclamped inductive turn-off RGS = 50 Ω  
energy  
Tj = 25˚C prior to surge  
Tj = 100˚C prior to surge  
-
-
-
510  
82  
13  
mJ  
mJ  
mJ  
1
WDSR  
Drain-source repetitive  
ID = 8 A; VDD 50 V; VGS = 10 V;  
unclamped inductive turn-off RGS = 50 ; Tj 150 ˚C  
energy  
1. Pulse width and frequency limited by Tj(max)  
November 1996  
1
Rev 1.000  

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