PHY1076-01
125Mbps to 2.7Gbps Laser Driver/
Post Amp with Digital Diagnostics
Features
Description
The PHY1076-01 is a combined Laser driver and
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Multi-rate from 125Mbps to 2.7Gbps
limiting amplifier with support for Digital Diagnostic
Monitoring for use within small form factor
modules for Fibre Channel, GbE and SONET/SDH
applications.
Laser driver output stage with 70mA max
modulation drive and 100mA bias current
Programmable mean power control loop
Temperature compensated modulation current
Integrated limiting amplifier with selectable
swing CML output
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The transmitter integrates a high speed output
stage with programmable bias and modulation
currents, controlled through
interface. The mean power control loop allows
connection in common anode configuration.
a
2-wire serial
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Programmable receiver low pass filter
Integrated Loss Of Signal function
Digital diagnostic mode compliant with SFF-
8472 using an external MCU
Stand-alone mode where device parameters
are loaded from an external EEPROM
-40°C to +95°C ambient operating range
36pin 6mm x 6mm QFN package
Eye safety logic
A Loss Of Signal (LOS) detector is included with
detection based on either the receiver photo
detector average current or received signal
modulation amplitude.
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When used in digital diagnostics mode the
integrated A/D converters measuring temperature,
TX Bias, Supply Voltage, RX Signal Strength and
Mean Power are read via a 2-wire serial interface.
An external Microcontroller Unit (MCU) is used for
calibrating real time diagnostic monitors and alarm
generation.
Applications
Fibre Channel 1x, 2x
Gigabit Ethernet, SONET/SDH
OC-3, OC-12, OC-48
Ref
LOS
MUX
RSSI
Voltage
Reg
Ref
Level
Detect
RXOUT+
RXIN+
RXIN-
Low Pass
Filter
O/P
RXOUT-
TXIN+
SA_SDA
RESET
VDD_RXO
VSS_RX
RXOUT-
RXOUT+
SDA
1
27 VDD_TX
VGG
LASER+
LASER-
VSS_TX
LASER+
LASER-
TXIN-
Driver
TSENSE
Temperature
Comp
Modulation
36QFN
LASER BIAS
TX_DISABLE
TX_FAULT
VSS_TX
VDD_TXO
VDD_TX
Safety
Logic
Mean Power
Control Loop
MPD
SHUTDOWN
SCL
SCL
SDA
SA_SDA
SA_SCL
Internal
Registers
& 2 Wire I/F
RREF
9
19
LASER_BIAS
Figure 1 - Outline Block Diagram
Figure 2 - Device Pin Out (Top View)
19-5684; Rev 9/12
1