Datasheet > PDM4M3120S15M

PDM4M3120S15M

更新时间： 2024-02-24 05:59:05

品牌	Logo	应用领域
IXYS		静态存储器
页数	文件大小	规格书
10页	108K
描述
SRAM Module, 1MX32, 15ns, CMOS, SIMM-72

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数据手册

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PDM4M3120S15M 数据手册

PRELIMINARY

PDM4M3120

Pin Conﬁguration⁽¹⁾

Pin Assignment

Signal

PD0 - Vss

I/O31-I/O0

A19-A0

CS4-CS1

Data Inputs/Outputs

Addresses

PD3

PD0

I/O0

I/O1

I/O2

I/O3

Vcc

PD2

Vss

PD1 - NC

PD2 - Vss

PD3 - NC

Chip Selects

Write Enable

Output Enable

Depth Identification

Power

PD1

I/O8

I/O9

I/O10

I/O11

PD3-PD0

Ground

I/O12

I/O13

I/O14

I/O15

Vss

I/O4

I/O5

I/O6

I/O7

A15

CS2

A14

CS1

ZIP, SIMM

TOP VIEW

CS4

A17

CS3

A16

Vss

I/O24

I/O25

I/O26

I/O27

I/O16

I/O17

I/O18

I/O19

A10

A11

A12

Vcc

A13

I/O20

I/O21

I/O22

I/O23

Vss

I/O28

I/O29

I/O30

I/O31

A18

A19

NOTE: 1. Pins 3, 4, 6, and 7 (PD0, PD1, PD02, and PD3

respectively) are read by the user to determine the

density of the module. If PD0 reads V , PD1 reads

NC, PD2 reads V , PD3 reads NC then the mod-

ule has a 1M depth.

Rev 1.1

123 4 5 6 7...10

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