Datasheet > PDM4M4050S10AM

PDM4M4050S10AM

更新时间： 2024-01-04 12:03:57

品牌	Logo	应用领域
IXYS		静态存储器
页数	文件大小	规格书
10页	216K
描述
SRAM

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技术参数
数据手册

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PDM4M4050S10AM 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.84
Is Samacsys：	N	Base Number Matches：	1

PDM4M4050S10AM 数据手册

PDM4M4050

256K x 32 BiCMOS/CMOS

Static RAM Module

The PDM4M4050 is packaged in a 64-pin FR-4 ZIP

(Zig-zag In-line vertical Package) or a 64-pin SIMM

(Single In-line Memory Module). The Angled SIMM

Features

■ High-density 8 megabit Static RAM module

■ Low proﬁle 64-pin ZIP, 64 -pin SIMM (Single In-

line Memory Module) or Angled SIMM.

■ Ultra fast access time: 10 ns (max.)

■ Surface mounted plastic components on an epoxy

laminate (FR-4) substrate

■ Single 5V (±10%) power supply

■ Multiple V pins and decoupling capacitors for

maximum noise immunity

■ Inputs/outputs directly TTL-compatible

_{conﬁguration allows 64 pins to be placed on a pack-}2

^{SIMM conﬁguration also allows use of edge mounted}3

age 3.50” long and 0.35” wide and 0.68” high. The

sockets to secure the module.

All inputs and outputs of the PDM4M4050 are TTL-

compatible and operate from a single 5V supply. Full

asynchronous circuitry requires no clocks or refresh

for operation and provides equal access and cycle

times for ease of use.

Two identiﬁcation pins (PD0 and PD1) are provided

for applications in which different density versions of

Description

the module are used. In this way, the target system

can read the respective levels of PD0 and PD1 to

determine a 256K depth.

The PDM4M4050 is a 256K x 32 static RAM module

constructed on an epoxy laminate (FR-4) substrate

using eight 256K x 4 static RAMs in plastic SOJ pack-

ages. Availability of four chips select lines (one for

each group of two RAMs) provides byte access.

Extremely fast speeds can be achieved due to the use

of 1 megabit static RAMs fabricated in Paradigm’s

high-performance, high-reliability technology. The

PDM4M4050 is available with access time as fast as

10 ns with minimal power consumption.

Functional Block Diagram

CS1

CS2

CS3

CS4

ADDRESS

256K x 32

RAM

I/O31-I/O0

Rev 2.2 - 7/17/97

8-45

12 3 4 5 6 7...10

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