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PDM4M4060S25AM PDF预览

PDM4M4060S25AM

更新时间: 2024-01-12 08:11:11
品牌 Logo 应用领域
IXYS 静态存储器内存集成电路
页数 文件大小 规格书
10页 200K
描述
SRAM Module, 256KX32, 25ns, CMOS, ANGLED, SIMM-72

PDM4M4060S25AM 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SIMM
包装说明:ANGLED, SIMM-72针数:72
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.65
最长访问时间:25 nsJESD-30 代码:R-XSMA-N72
内存密度:8388608 bit内存集成电路类型:SRAM MODULE
内存宽度:32功能数量:1
端子数量:72字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX32封装主体材料:UNSPECIFIED
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子位置:SINGLE处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

PDM4M4060S25AM 数据手册

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PDM4M4060  
256K x 32 CMOS  
Static RAM Module  
1
The PDM4M4060 is packaged in a 72-lead SIMM  
(Single In-line Memory Module). The SIMM  
configuration allows 72 leads to be placed on a  
Features  
High-density 8 megabit Static RAM module)  
Low profile 72-lead SIMM and Angled SIMM  
(Single In-line Memory Module)  
Very fast access time: 10 ns (max.)  
Surface mounted plastic components on an epoxy  
laminate (FR-4) substrate  
Single 5V (±10%) power supply  
Multiple V pins and decoupling capacitors for  
maximum noise immunity  
Inputs/outputs directly TTL compatible  
package 4.25” long and 0.35” wide. At only 0.650” 2  
high, this low-profile package is ideal for systems  
with minimum board spacing. The SIMM  
configuration allows use of angled sockets to reduce  
the effective module height further. The Angled 3  
SIMM configuration allows 72 leads to be placed on a  
package 4.255” long and 0.35” wide. At only 0.680”  
high, this low-profile package is ideal for systems  
SS  
4
with minimum board spacing.  
All inputs and outputs of the PDM4M4060 are TTL  
compatible and operate from a single 5V supply. Full  
Description  
asynchronous circuitry requires no clock or refresh for  
operation and provides equal access and cycle times 5  
The PDM4M4060 is a 256K x 32 static RAM module  
constructed on an epoxy laminate (FR-4) substrate  
using eight 256K x 4 static RAMs in plastic SOJ pack-  
ages. Availability of four chip select lines (one for  
each of two RAMs) provides byte access. The  
PDM4M4060 is available with access times as fast as  
15 ns with minimal power consumption.  
for ease of use.  
Four identification pins (PD3-PD0) are provided for  
applications in which different density versions of the  
module are used. In this way, the target system can  
read the respective levels of PD3-PD0 to determine a  
256K depth.  
6
7
Functional Block Diagram  
CS1  
CS2  
CS3  
CS4  
9
18  
ADDRESS  
WE  
2
PD  
256K x 32  
10  
11  
12  
OE  
8
8
8
8
I/O31-I/O0  
Rev 2.2

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