Datasheet > PDM4M4050S10AM

PDM4M4050S10AM

更新时间： 2024-01-20 12:22:27

品牌	Logo	应用领域
IXYS		静态存储器
页数	文件大小	规格书
10页	216K
描述
SRAM

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技术参数
数据手册

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PDM4M4050S10AM 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.84
Is Samacsys：	N	Base Number Matches：	1

PDM4M4050S10AM 数据手册

PDM4M4050

DC Electrical Characteristics (V = 5.0V ± 5%, T = 0°C to 70°C)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

Input Leakage Current

(Address)

= Max.,V = V to V

—

µA

Input Leakage Current

(Data)

= Max., V = V to V

—

µA

Output Leakage Current

= V to V , V = Max.,

SS CC CC

OUT

CS = V

Output Low Voltage

Output High Voltage

Input High Voltage

Input Low Voltage

= 8 mA, V = Min.

—

0.4

—

= –4 mA, V = Min.

2.4

2.2

6.0

0.8

(1)

–0.5

NOTE 1. V = –1.5V for pulse widths less than 10 ns, once per cycle.

Power Supply Characteristics

(1)

10 ns - 15 ns

Max

20 ns - 25 ns

Max

Unit

Symbol

Parameter

Operating Current

1600

480

1360

480

CS = V , V = Max., f = f , Outputs Open

MAX

Standby Current

CS ≥ V , V = Max., f = f , Outputs Open

MAX

Full Standby Current CS ≥ V – 0.2V,

320

120

SB1

f = 0, V > V – 0.2V or < 0.2V, Outputs Open

NOTE 1. Preliminary speciﬁcation only.

Capacitance⁽¹⁾(T = +25°C, f = 1.0 MHz)

Symbol

Parameter

Input Capacitance, (CS) V = 0V

Max.

Unit

IN(C)

IN(A)

I/O

Input Capacitance, (Address and Control) V = 0V

I/O Capacitance V

= 0V

OUT

NOTE 1. This parameter is determined by device characteristics but is not production tested.

8-48

Rev 2.2 - 7/17/97

1 2 345 6 7...10

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