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NTB10N40/D PDF预览

NTB10N40/D

更新时间： 2024-02-09 20:20:51
品牌 Logo 应用领域
其他 - ETC 晶体晶体管功率场效应晶体管
页数 文件大小 规格书
4页 76K
描述
TMOS 7 E-FET? Power Field Effect Transistor

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中文翻译

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NTB10N40/D 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：D2PAK-3针数：3
Reach Compliance Code：not_compliantECCN代码：EAR99
风险等级：5.8雪崩能效等级（Eas）：500 mJ
外壳连接：DRAIN配置：SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：400 V最大漏极电流 (Abs) (ID)：10 A
最大漏极电流 (ID)：10 A最大漏源导通电阻：0.5 Ω
FET 技术：METAL-OXIDE SEMICONDUCTORJESD-30 代码：R-PSSO-G2
JESD-609代码：e0元件数量：1
端子数量：2工作模式：ENHANCEMENT MODE
最高工作温度：150 °C封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：N-CHANNEL
最大功率耗散 (Abs)：142 W最大脉冲漏极电流 (IDM)：35 A
认证状态：Not Qualified子类别：FET General Purpose Powers
表面贴装：YES端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子位置：SINGLE
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

NTB10N40/D 数据手册

 浏览型号NTB10N40/D的Datasheet PDF文件第2页浏览型号NTB10N40/D的Datasheet PDF文件第3页浏览型号NTB10N40/D的Datasheet PDF文件第4页 
Preferred Device  
N–Channel Enhancement–Mode  
Silicon Gate  
http://onsemi.com  
TMOS POWER FET  
10 AMPERES  
400 VOLTS  
This advanced TMOS E–FET is designed to withstand high energy  
in the avalanche and commutation modes. This new energy efficient  
design also offers a drain–to–source diode with a fast recovery time.  
Designed for low voltage, high speed switching applications in power  
supplies, converters and PWM motor controls, these devices are  
particularly well suited for bridge circuits where diode speed and  
commutating safe operating areas are critical and offer additional  
safety margin against unexpected voltage transients.  
R
= 0.5 Ω  
DS(on)  
N–Channel  
D
New Features of TMOS 7  
• Ultra Low On–Resistance Provides Higher Efficiency  
• Reduced Gate Charge  
Features Common to TMOS 7 and TMOS E–FETS  
• Avalanche Energy Specified  
G
• Diode Characterized for Use in Bridge Circuits  
S
• I  
and V  
Specified at Elevated Temperature  
DS(on)  
DSS  
MARKING  
DIAGRAMS  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
C
Rating  
Drain–Source Voltage  
Symbol  
Value  
Unit  
V
DSS  
400  
400  
Vdc  
Vdc  
Vdc  
4
2
D PAK  
CASE 418B  
STYLE 2  
NTB10N40  
YWW  
Drain–Gate Voltage (R  
= 1.0 MΩ)  
V
DGR  
GS  
1
2
Gate–Source Voltage  
— Continuous  
3
V
20  
40  
GS  
— Non–Repetitive (t  
10 ms)  
p
V
GSM  
Drain — Continuous  
— Continuous @ 100°C  
I
10  
7.5  
35  
Adc  
YY, Y = Year  
WW, W = Work Week  
D
I
D
— Single Pulse (t  
10 µs)  
p
I
DM  
PIN ASSIGNMENT  
Total Power Dissipation  
Derate above 25°C  
P
142  
1.14  
Watts  
W/°C  
D
1
Gate  
Drain  
Operating and Storage Temperature  
Range  
T , T  
J stg  
–55 to  
150  
°C  
2
3
4
Source  
Single Drain–to–Source Avalanche  
E
AS  
500  
mJ  
Energy — Starting T = 25°C  
J
GS  
Drain  
(V  
= 100 Vdc, V  
= 10 Vdc,  
DD  
I
L
= 10 A, L = 10 mH, R = 25 Ω)  
G
Thermal Resistance  
— Junction–to–Case  
°C/W  
R
R
R
0.88  
62.5  
50  
ORDERING INFORMATION  
θJC  
θJA  
θJA  
— Junction–to–Ambient  
— Junction–to–Ambient (Note 1.)  
Device  
Package  
Shipping  
50 Units/Rail  
Maximum Lead Temperature for Soldering  
Purposes, 1/8″ from case for 10 seconds  
T
260  
°C  
L
2
D PAK  
NTB10N40  
2
1. When surface mounted to an FR4 board using the minimum recommended  
pad size.  
NTB10N40T4  
D PAK  
800 Tape & Reel  
Preferred devices are recommended choices for future use  
and best overall value.  
This document contains information on a product under development. ON Semiconductor  
reserves the right to change or discontinue this product without notice.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
June, 2000 – Rev. 0  
NTB10N40/D  
1234

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