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NLAST44599_10 PDF预览

NLAST44599_10

更新时间: 2024-09-13 07:20:23
品牌 Logo 应用领域
安森美 - ONSEMI 开关光电二极管
页数 文件大小 规格书
13页 136K
描述
Low Voltage Single Supply Dual DPDT Analog Switch

NLAST44599_10 数据手册

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NLAST44599  
Low Voltage Single Supply  
Dual DPDT Analog Switch  
The NLAST44599 is an advanced CMOS dualindependent  
DPDT (double poledouble throw) analog switch, fabricated with  
silicon gate CMOS technology. It achieves highspeed propagation  
delays and low ON resistances while maintaining CMOS lowpower  
dissipation. This DPDT controls analog and digital voltages that may  
http://onsemi.com  
MARKING  
vary across the full powersupply range (from V to GND).  
CC  
The device has been designed so the ON resistance (R ) is much  
DIAGRAMS  
ON  
lower and more linear over input voltage than R of typical CMOS  
ON  
16  
analog switches.  
1
QFN16  
MN SUFFIX  
CASE 485G  
T
ALYWG  
G
The channelselect input structure provides protection when  
voltages between 0 V and 5.5 V are applied, regardless of the supply  
voltage. This input structure helps prevent device destruction caused  
by supply voltage input/output voltage mismatch, battery backup,  
hot insertion, etc.  
The NLAST44599 can also be used as a quad 2to1 multiplexer−  
demultiplexer analog switch with two Select pins that each controls  
two multiplexerdemultiplexers.  
16  
NLAT  
4459  
ALYWG  
G
TSSOP16  
DT SUFFIX  
CASE 948F  
16  
1
Select Pins Compatible with TTL Levels  
Channel Select Input Overvoltage Tolerant to 5.5 V  
Fast Switching and Propagation Speeds  
BreakBeforeMake Circuitry  
Low Power Dissipation: I = 2 A (Max) at T = 25°C  
Diode Protection Provided on Channel Select Input  
Improved Linearity and Lower ON Resistance over Input Voltage  
Latchup Performance Exceeds 300 mA  
1
A
L
Y
W
G
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
CC  
A
= PbFree Package  
(Note: Microdot may be in either location)  
ESD Performance: Human Body Model > 2000 V;  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 10 of this data sheet.  
Machine Model > 100 V  
Chip Complexity: 158 FETs  
PbFree Packages are Available  
©
Semiconductor Components Industries, LLC, 2010  
1
Publication Order Number:  
November, 2010 Rev. 9  
NLAST44599/D  

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