Datasheet > NE321000_01

NE321000_01

更新时间： 2024-11-07 03:46:43

品牌	Logo	应用领域
CEL		/
页数	文件大小	规格书
6页	136K
描述
ULTRA LOW NOISE PSEUDOMORPHIC HJ FET

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中文翻译

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数据手册

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NE321000_01 数据手册

ULTRA LOW NOISE

PSEUDOMORPHIC HJ FET

NE321000

NOISE FIGURE & ASSOCIATED GAIN vs.

DRAIN CURRENT

FEATURES

• SUPER LOW NOISE FIGURE:

DS = 2 V

0.35 dB Typ at f = 12 GHz

f = 12 GHz

• HIGH ASSOCIATED GAIN:

13.0 dB Typ at f = 12 GHz

• GATE LENGTH: ≤0.2 µm

• GATE WIDTH: 160 µm

2.0

1.5

1.0

0.5

DESCRIPTION

NEC's NE321000 is a Hetero-Junction FET chip that utilizes

the junction between Si-doped AlGaAs and undoped InGaAs

to create high electron mobility. Its excellent low noise figure

and high associated gain make it suitable for commercial,

industrial and space applications.

Drain Current, ID (mA)

NEC's stringent quality assurance and test procedures assure

the highest reliability and performance.

ELECTRICAL CHARACTERISTICS (TA = 25°C)

PART NUMBER

PACKAGE OUTLINE

NE321000

CHIP

SYMBOLS

PARAMETERS AND CONDITIONS

Noise Figure, VDS = 2 V, ID = 10 mA, f = 12 GHz

Associated Gain, VDS = 2 V, ID = 10 mA, f = 12 GHz

Saturated Drain Current, VDS = 2 V, VGS = 0 V

Pinch-off Voltage, VDS = 2 V, ID = 100 µA

UNITS

MIN

TYP

0.35

13.5

MAX

0.45

12.0

IDSS

-0.2

-0.7

-2.0

Transconductance, VDS = 2 V, ID = 10 µA

µA

IGSO

Gate to Source Leakage Current, VGS = -3 V

0.5

Note:

1. RF performance is determined by packaging and testing 10 samples per wafer. Wafer rejection criteria for standard devices is 2 rejects per

10 samples.

California Eastern Laboratories

12 3 4 5 6

中文翻译

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