Datasheet > NE32500N

NE32500N

更新时间： 2024-09-25 03:46:43

品牌	Logo	应用领域
CEL		晶体放大器晶体管
页数	文件大小	规格书
3页	87K
描述
C TO KA BAND SUPER LOW NOISE AMPLIFIER N-CHANNEL HJ FET CHIP

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数据手册

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NE32500N 数据手册

NEC's C TO KA BAND

SUPER LOW NOISE AMPLIFIER

N-CHANNEL HJ FET CHIP

NE32500

FEATURES

OUTLINE DIMENSIONS (Units in µm)

• SUPER LOW NOISE FIGURE:

0.45 dB TYP at 12 GHz

CHIP

5.5

36.5

• HIGH ASSOCIATED GAIN:

12.5 dB TYP at 12 GHz

• GATE LENGTH: LG = 0.20 µm

• GATE WIDTH: WG = 200 µm

Drain

350

DESCRIPTION

Source

76.5

NEC's NE32500 is a Hetero-Junction FET chip that uses the

junction between Si-doped AlGaAs and undoped InGaAs to

create very high mobility electrons. Its excellent low noise figure

and high associated gain make it suitable for commercial

systems and industrial applications.

100.5

Gate

46.5

NEC's stringent quality assurance and test procedures assure

the highest reliability and performance.

49.5

350

Thickness = 140 µm

Bonding Area

ELECTRICAL CHARACTERISTICS (TA = 25°C)

PART NUMBER

PACKAGE OUTLINE

NE32500

00 (Chip)

SYMBOLS

PARAMETERS AND CONDITIONS

Noise Figure, VDS = 2 V, IDS = 10 mA, f = 12 GHz

Associated Gain, VDS = 2 V, IDS = 10 mA, f = 12 GHz

Saturated Drain Current, VDS = 2 V,VGS = 0 V

Transconductance, VDS = 2 V, ID = 10 mA

UNITS

MIN

TYP

0.45

12.5

MAX

0.55

11.0

IDSS

µA

IGSO

Gate to Source Leakage Current, VGS = -3 V

Gate to Source Cutoff Voltage, VDS = 2 V, ID = 100 µA

Thermal Resistance¹(Channel to Case)

0.5

10.0

-2.0

260

VGS(off)

RTH (CH-C)

-0.2

-0.7

°C/W

Note:

1. RF performance is determined by packaging and testing 10 chips per wafer.

Wafer rejection criteria for standard devices is 2 rejects per 10 samples.

California Eastern Laboratories

12 3

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