5秒后页面跳转
NCP5201/D PDF预览

NCP5201/D

更新时间: 2024-09-25 23:53:27
品牌 Logo 应用领域
其他 - ETC 双倍数据速率控制器
页数 文件大小 规格书
10页 68K
描述
Dual Output DDR Power Controller

NCP5201/D 数据手册

 浏览型号NCP5201/D的Datasheet PDF文件第2页浏览型号NCP5201/D的Datasheet PDF文件第3页浏览型号NCP5201/D的Datasheet PDF文件第4页浏览型号NCP5201/D的Datasheet PDF文件第5页浏览型号NCP5201/D的Datasheet PDF文件第6页浏览型号NCP5201/D的Datasheet PDF文件第7页 
NCP5201  
Dual Output  
DDR Power Controller  
The NCP5201 Dual DDR Power Controller is specifically  
designed as a total power solution for a high current DDR memory  
system. This IC combines the efficiency of a PWM controller for the  
VDDQ supply with the simplicity of a linear regulator for the VTT  
memory termination voltage. The secondary regulator (VTT) is  
designed to automatically track at half the primary regulator voltage  
(VDDQ). An internal power good voltage monitor tracks both  
VDDQ and VTT outputs and notifies the user in the event of a fault  
on either output. Protective features include soft start circuitry,  
undervoltage monitoring of VCC and VSTBY, and thermal  
shutdown. The IC is packaged in a 5 × 6 QFN−18.  
http://onsemi.com  
MARKING  
DIAGRAM  
1
NCP5201  
1
AWLYYWW  
18−LEAD QFN, 5 x 6 mm  
MN SUFFIX  
Features  
CASE 505  
Incorporates VDDQ, VTT Regulators  
Internal Switching Standby Regulator for VDDQ  
All External Power MOSFETs Are N−Channel  
Adjustable VDDQ  
NCP5201= Specific Device Code  
A
= Assembly Location  
= Wafer Lot  
WL  
YY  
WW  
= Year  
VTT Tracks VDDQ/2  
= Work Week  
Fixed Switching Frequency of 250 kHz for VDDQ in Normal Mode  
Doubled Switching Frequency (500 kHz) for Standby Mode  
Soft Start Protection for VDDQ  
PIN CONNECTIONS  
Undervoltage Monitor  
Short−Circuit Protection for Both VDDQ and VTT Outputs  
Thermal Shutdown  
FBDDQ  
FBVTT  
PGND  
VSTBY  
VTT  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
10  
SS  
COMP  
VCC  
TGDDQ  
BGDDQ  
SDDQ  
AGND  
S3_EN  
PWRGD  
Housed in a space saving 5 × 6 QFN−18  
Typical Applications  
VTT  
OCDDQ  
VDDQ  
NC  
DDR Termination Voltage  
Active Termination Busses (SSTL−2, SSTL−3)  
NOTE: Pin 19 is the thermal pad on the bottom of  
the device.  
ORDERING INFORMATION  
Device  
Package  
Shipping  
NCP5201MN  
18−LeadQFN*  
61 Units/Rail  
NCP5201MNR2 18−Lead QFN* 2500 Units/Reel  
*5 × 6 mm  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specifications  
Brochure, BRD8011/D.  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
January, 2004 − Rev. 6  
NCP5201/D  

与NCP5201/D相关器件

型号 品牌 获取价格 描述 数据表
NCP5201_06 ONSEMI

获取价格

Dual Output DDR Power Controller
NCP5201MN ONSEMI

获取价格

Dual Output DDR Power Controller
NCP5201MNG ONSEMI

获取价格

Dual Output DDR Power Controller
NCP5201MNR2 ONSEMI

获取价格

Dual Output DDR Power Controller
NCP5201MNR2G ONSEMI

获取价格

Dual Output DDR Power Controller
NCP5203 ONSEMI

获取价格

2-in-1 DDR Power Controller
NCP5203/D ETC

获取价格

2-in-1 DDR Power Controller
NCP5203MNR2 ONSEMI

获取价格

2-in-1 DDR Power Controller
NCP5203MNR2G ONSEMI

获取价格

2-in-1 DDR Power Controller
NCP5208 ONSEMI

获取价格

DDR-I/II Termination Regulator