Order this document
by MTP3N100E/D
SEMICONDUCTOR TECHNICAL DATA
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
3.0 AMPERES
1000 VOLTS
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
R
= 4.0 OHM
DS(on)
•
•
•
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
D
•
•
Diode is Characterized for Use in Bridge Circuits
I
and V Specified at Elevated Temperature
DSS
DS(on)
G
CASE 221A–06, Style 5
TO–220AB
S
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Symbol
Value
1000
1000
Unit
Vdc
Vdc
Drain–Source Voltage
V
DSS
Drain–Gate Voltage (R
= 1.0 MΩ)
Gate–Source Voltage — Continuous
V
DGR
GS
V
± 20
± 40
Vdc
Vpk
GS
Gate–Source Voltage — Non–Repetitive (t ≤ 10 ms)
V
GSM
p
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (t ≤ 10 µs)
I
I
3.0
2.4
9.0
Adc
Apk
D
D
I
p
DM
Total Power Dissipation
Derate above 25°C
P
D
125
1.0
Watts
W/°C
Operating and Storage Temperature Range
T , T
stg
–55 to 150
245
°C
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C
E
AS
mJ
J
(V
DD
= 150 Vdc, V = 10 Vdc, I = 7.0 Apk, L = 10 mH, R = 25 Ω)
GS L G
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
R
θJC
R
θJA
1.00
62.5
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
T
L
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 3
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1995
1