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MT9040 PDF预览

MT9040

更新时间: 2024-01-03 18:51:42
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
27页 410K
描述
T1/E1 Synchronizer

MT9040 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP48,.4针数:48
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84JESD-30 代码:R-PDSO-G48
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:3.3 V认证状态:Not Qualified
子类别:Other Telecom ICs最大压摆率:50 mA
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL

MT9040 数据手册

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MT9040  
Data Sheet  
Pin Description (continued)  
Pin #  
Name  
Description  
12  
F0o  
Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low framing  
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS  
operation at 2.048Mb/s and 4.096Mb/s. See Figure 11.  
13  
14  
15  
RSP  
TSP  
F8o  
Receive Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse, which  
marks the beginning of an ST-BUS frame. This is typically used for connection to the Siemens  
MUNICH-32 device. See Figure 12.  
Transmit Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse,  
which marks the beginning of an ST-BUS frame. This is typically used for connection to the  
Siemens MUNICH-32 device. See Figure 12.  
Frame Pulse (CMOS Output). This is an 8kHz 122ns active high framing pulse, which marks  
the beginning of a frame. See Figure 11.  
16  
18  
C1.5o Clock 1.544MHz (CMOS Output). This output is used in T1 applications.  
LOCK Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to  
the input reference.  
19  
20  
C2o  
C4o  
Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s.  
Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s  
and 4.096Mb/s.  
21  
22  
C19o Clock 19.44MHz (CMOS Output). This output is used in OC3/STS3 applications.  
FLOCK Fast Lock Mode (Input). Set high to allow the PLL to quickly lock to the input reference (less  
than 500 ms locking time).  
24  
25  
26  
IC  
Internal Connection. Tie low for normal operation.  
C8o  
Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s.  
C16o Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation with a  
16.384MHz clock.  
27  
29  
C6o  
IM  
Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.  
Impairment Monitor (CMOS Output). A logic high on this pin indicates that the Input  
Impairment Monitor has automatically put the device into Freerun Mode.  
30  
32  
IC  
NC  
IC  
Internal Connection. Tie high for normal operation.  
No Connection. Leave open circuit.  
33,34,  
42  
Internal Connection. Tie low for normal operation.  
36  
MS  
Mode/Control Select (Input). This input determines the state (Normal or Freerun) of  
operation. The logic level at this input is gated in by the rising edge of F8o. See Table 2.  
37, 39  
40  
IC  
Internal Connection. Tie low for normal operation.  
FS2  
Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four possible  
frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the REF input. See  
Table 1.  
41  
44  
FS1  
Frequency Select 1 (Input). See pin description for FS2.  
TDO Test Serial Data Out (CMOS Output). JTAG serial data is output on this pin on the falling  
edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled.  
3
Zarlink Semiconductor Inc.  

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