MT9042C
Multitrunk System Synchronizer
Data Sheet
November 2005
Features
•
Meets jitter requirements for: AT&T TR62411
Ordering Information
Stratum 3, 4 and Stratum 4 Enhanced for DS1
interfaces; and for ETSI ETS 300 011, TBR 4,
TBR 12 and TBR 13 for E1 interfaces
MT9042CP
MT9042CPR 28 Pin PLCC
MT9042CP1
28 Pin PLCC
Tubes
Tape & Reel
28 Pin PLCC* Tubes
•
Provides C1.5, C3, C2, C4, C8 and C16 output
clock signals
MT9042CPR1 28 Pin PLCC* Tape & Reel
*Pb Free Matte Tin
•
•
Provides 8 kHz ST-BUS framing signals
-40°C to +85°C
Selectable 1.544 MHz, 2.048 MHz or 8 kHz
input reference signals
Description
•
•
•
Accepts reference inputs from two independent
sources
The MT9042C Multitrunk System Synchronizer
contains a digital phase-locked loop (DPLL), which
provides timing and synchronization signals for
multitrunk T1 and E1 primary rate transmission links.
Provides bit error free reference switching -
meets phase slope and MTIE requirements
Operates in either Normal, Holdover and
Freerun modes
The MT9042C generates ST-BUS clock and framing
signals that are phase locked to either a 2.048 MHz,
1.544 MHz, or 8 kHz input reference.
Applications
The MT9042C is compliant with AT&T TR62411
Stratum 3, 4 and 4 Enhanced, and ETSI ETS 300 011.
It will meet the jitter tolerance, jitter transfer, intrinsic
jitter, frequency accuracy, holdover accuracy, capture
range, phase slope and MTIE requirements for these
specifications.
•
Synchronization and timing control for
multitrunk T1 and E1 systems
•
•
ST-BUS clock and frame pulse sources
Primary Trunk Rate Converters
TRST
VDD
VSS
Virtual
Refer-
ence
C1.5o
C3o
C2o
C4o
C8o
C16o
F0o
OSCi
TIE
Master
Clock
Corrector
Circuit
DPLL
OSCo
Output
Interface
Circuit
Selected
Refer-
ence
State
Select
PRI
Reference
Select
F8o
F16o
SEC
MUX
Input
Impairment
Monitor
TIE
Correcto
r Enable
Reference
State
Select
Feedback
RSEL
LOS1
LOS2
Frequency
Select
MUX
Automatic/Manual
Control State Machine
Guard Time
Circuit
FS1
FS2
MS1
MS2
RST
GTo
GTi
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.