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MT9040 PDF预览

MT9040

更新时间: 2024-01-22 07:25:40
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
27页 410K
描述
T1/E1 Synchronizer

MT9040 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP48,.4针数:48
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84JESD-30 代码:R-PDSO-G48
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:3.3 V认证状态:Not Qualified
子类别:Other Telecom ICs最大压摆率:50 mA
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL

MT9040 数据手册

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MT9040  
Data Sheet  
Pin Description (continued)  
Pin #  
Name  
Description  
Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin.  
45  
TDI  
This pin is internally pulled up to VDD  
.
46  
TRST Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the  
Test-Logic-Reset state. If not used, this pin should be held low.  
47  
48  
TCK  
Test Clock (Input). Provides the clock to the JTAG test logic.  
TMS Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP controller.  
Functional Description  
The MT9040 is a T1/E1 Trunk Synchronizer, providing timing (clock) and synchronization (frame) signals to  
interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block diagram which  
is described in the following sections.  
Frequency Select MUX Circuit  
The MT9040 operates on the falling edge of the reference. It operates with one of four possible input reference  
frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). The frequency select inputs (FS1 and FS2) determine  
which of the four frequencies may be used at the reference input. A reset (RST) must be performed after every  
frequency select input change. See Table 1.  
FS2  
FS1  
Input Frequency  
0
0
1
0
1
19.44MHz  
8kHz  
0
1
1
1.544MHz  
2.048MHz  
Table 1 - Input Frequency Selection  
Digital Phase Lock Loop (DPLL)  
As shown in Figure 3, the DPLL of the MT9040 consists of a Phase Detector, Loop Filter, Digitally Controlled  
Oscillator and a Control Circuit.  
Phase Detector - the Phase Detector compares the reference signal with the feedback signal from the Frequency  
Select MUX circuit, and provides an error signal corresponding to the phase difference between the two. This error  
signal is passed to the Loop Filter. The Frequency Select MUX allows the proper feedback signal to be externally  
selected (e.g., 8kHz, 1.544MHz, 2.048MHz or 19.44MHz).  
4
Zarlink Semiconductor Inc.  

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