Datasheet > MT58V1MV18PF-6

MT58V1MV18PF-6

更新时间： 2024-11-08 04:52:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
34页	535K
描述
Cache SRAM, 1MX18, 3.5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165

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中文翻译

获取价格

数据手册

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MT58V1MV18PF-6 数据手册

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

MT58L1MY18P, MT58V1MV18P,

MT58L512Y32P, MT58V512V32P,

18Mb SYNCBURST^™

SRAM

MT58L512Y36P, MT58V512V36P

3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V I/O

Features

Figure 1: 100-Pin TQFP

JEDEC-Standard MS-026 BHA (LQFP)

•

Fast clock and OE# access times

Single 3.3V ±± percent or 2.±V ±± percent power

supply

•

Separate 3.3V ±± percent or 2.±V ±± percent isolated

output buffer supply (VDDQ)

•

SNOOZE MODE for reduced-power standby

Single-cycle deselect (Pentium^®BSRAM-

compatible)

•

Common data inputs and data outputs

Individual byte write control and global write

Three chip enables for simple depth expansion and

address pipelining

•

Clock-controlled and registered addresses, data

I/Os, and control signals

•

Internally self-timed WRITE cycle

Burst control (interleaved or linear burst)

Low capacitive bus loading

Figure 2: 165-Ball FBGA

JEDEC-Standard MS-216 (Var. CAB-1)

TQFP

Options

Marking

•

Timing (Access/Cycle/MHz)

3.1ns/±ns/200 MHz

3.±ns/6ns/166 MHz

4.2ns/7.±ns/133 MHz

±ns/10ns/100 MHz

Configurations

3.3V VDD, 3.3V or 2.±V I/O

1 Meg x 18

-±

-6

-7.±

-10

•

MT±8L1MY18P

MT±8L±12Y32P

MT±8L±12Y36P

±12K x 32

±12K x 36

Part Number Example:

2.±V VDD, 2.±V I/O

1 Meg x 18

±12K x 32

±12K x 36

Packages

MT58L512Y36PT-10

MT±8V1MV18P

MT±8V±12V32P

MT±8V±12V36P

General Description

The Micron^®SyncBurst™ SRAM family employs

high-speed, low-power CMOS designs that are fabri-

cated using an advanced CMOS process.

•

100-pin TQFP

16±-ball, 13mm x 1±mm FBGA

Operating Temperature Range

Commercial (0ºC ? T_A? +70ºC)

F¹

Micron’s 18Mb SyncBurst SRAMs integrate a 1 Meg x

18, ±12K x 32, or ±12K x 36 SRAM core with advanced

synchronous peripheral circuitry and a 2-bit burst

counter. All synchronous inputs pass through registers

controlled by a positive-edge-triggered single-clock

input (CLK). The synchronous inputs include all

addresses, all data inputs, active LOW chip enable

(CE#), two additional chip enables for easy depth

expansion (CE2, CE2#), burst control inputs (ADSC#,

None

IT²

Industrial (-40ºC ? T_A? +8±ºC)

NOTE:

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

2. Contact factory for availability of Industrial Temperature

devices.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

12 3 4 5 6 7...34

中文翻译

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与MT58V1MV18PF-6相关器件

型号	品牌	获取价格	描述	数据表
MT58V1MV18PT-10	CYPRESS	获取价格	Cache SRAM, 1MX18, 5ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58V1MV18PT-6	CYPRESS	获取价格	Cache SRAM, 1MX18, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58V1MV18PT-7.5	CYPRESS	获取价格	Cache SRAM, 1MX18, 4ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58V512V32D	MICRON	获取价格	16Mb SYNCBURST⑩ SRAM
MT58V512V32DT-7.5	ROCHESTER	获取价格	512KX32 CACHE SRAM, 4ns, PQFP100, PLASTIC, TQFP-100
MT58V512V32FF-10	CYPRESS	获取价格	Cache SRAM, 512KX32, 10ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
MT58V512V32FF-7.5	CYPRESS	获取价格	Cache SRAM, 512KX32, 7.5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
MT58V512V32FF-8.5	CYPRESS	获取价格	Cache SRAM, 512KX32, 8.5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
MT58V512V32FT-10	CYPRESS	获取价格	Cache SRAM, 512KX32, 10ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58V512V32FT-6.8	CYPRESS	获取价格	Cache SRAM, 512KX32, 6.8ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100

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