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MRF1518T1 PDF预览

MRF1518T1

更新时间: 2024-01-07 18:15:30
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 晶体射频场效应晶体管功率场效应晶体管放大器
页数 文件大小 规格书
20页 754K
描述
RF Power Field Effect Transistor

MRF1518T1 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SMALL OUTLINE, R-PQSO-N4针数:4
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8541.29.00.75风险等级:5.1
Is Samacsys:N外壳连接:SOURCE
配置:SINGLE最小漏源击穿电压:40 V
最大漏极电流 (Abs) (ID):4 A最大漏极电流 (ID):4 A
FET 技术:METAL-OXIDE SEMICONDUCTOR最高频带:ULTRA HIGH FREQUENCY BAND
JESD-30 代码:R-PQSO-N4JESD-609代码:e0
湿度敏感等级:1元件数量:1
端子数量:4工作模式:ENHANCEMENT MODE
最高工作温度:150 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260极性/信道类型:N-CHANNEL
最大功率耗散 (Abs):62.5 W认证状态:Not Qualified
子类别:FET General Purpose Power表面贴装:YES
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子位置:QUAD处于峰值回流温度下的最长时间:40
晶体管应用:AMPLIFIER晶体管元件材料:SILICON
Base Number Matches:1

MRF1518T1 数据手册

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APPLICATIONS INFORMATION  
DESIGN CONSIDERATIONS  
This device is a common-source, RF power, N-Channel  
enhancement mode, Lateral Metal-Oxide Semiconductor  
Field-Effect Transistor (MOSFET). Freescale Application  
Note AN211A, “FETs in Theory and Practice”, is suggested  
reading for those not familiar with the construction and char-  
acteristics of FETs.  
This surface mount packaged device was designed pri-  
marily for VHF and UHF portable power amplifier applica-  
tions. Manufacturability is improved by utilizing the tape and  
reel capability for fully automated pick and placement of  
parts. However, care should be taken in the design process  
to insure proper heat sinking of the device.  
drain-source voltage under these conditions is termed  
DS(on). For MOSFETs, VDS(on) has a positive temperature  
coefficient at high temperatures because it contributes to the  
V
power dissipation within the device.  
BVDSS values for this device are higher than normally re-  
quired for typical applications. Measurement of BVDSS is not  
recommended and may result in possible damage to the de-  
vice.  
GATE CHARACTERISTICS  
The gate of the RF MOSFET is a polysilicon material, and  
is electrically isolated from the source by a layer of oxide.  
The DC input resistance is very high - on the order of 109 Ω  
— resulting in a leakage current of a few nanoamperes.  
Gate control is achieved by applying a positive voltage to  
the gate greater than the gate-to-source threshold voltage,  
The major advantages of Lateral RF power MOSFETs in-  
clude high gain, simple bias systems, relative immunity from  
thermal runaway, and the ability to withstand severely mis-  
matched loads without suffering damage.  
VGS(th)  
.
Gate Voltage Rating — Never exceed the gate voltage  
rating. Exceeding the rated VGS can result in permanent  
damage to the oxide layer in the gate region.  
MOSFET CAPACITANCES  
The physical structure of a MOSFET results in capacitors  
between all three terminals. The metal oxide gate structure  
determines the capacitors from gate-to-drain (Cgd), and  
gate-to-source (Cgs). The PN junction formed during fab-  
rication of the RF MOSFET results in a junction capacitance  
from drain-to-source (Cds). These capacitances are charac-  
terized as input (Ciss), output (Coss) and reverse transfer  
(Crss) capacitances on data sheets. The relationships be-  
tween the inter-terminal capacitances and those given on  
data sheets are shown below. The Ciss can be specified in  
two ways:  
Gate Termination — The gates of these devices are es-  
sentially capacitors. Circuits that leave the gate open-cir-  
cuited or floating should be avoided. These conditions can  
result in turn-on of the devices due to voltage build-up on  
the input capacitor due to leakage currents or pickup.  
Gate Protection — These devices do not have an internal  
monolithic zener diode from gate-to-source. If gate protec-  
tion is required, an external zener diode is recommended.  
Using a resistor to keep the gate-to-source impedance low  
also helps dampen transients and serves another important  
function. Voltage transients on the drain can be coupled to  
the gate through the parasitic gate-drain capacitance. If the  
gate-to-source impedance and the rate of voltage change  
on the drain are both high, then the signal coupled to the gate  
may be large enough to exceed the gate-threshold voltage  
and turn the device on.  
1. Drain shorted to source and positive voltage at the gate.  
2. Positive voltage of the drain in respect to source and zero  
volts at the gate.  
In the latter case, the numbers are lower. However, neither  
method represents the actual operating conditions in RF ap-  
plications.  
DC BIAS  
Since this device is an enhancement mode FET, drain cur-  
rent flows only when the gate is at a higher potential than the  
source. RF power FETs operate optimally with a quiescent  
drain current (IDQ), whose value is application dependent.  
This device was characterized at IDQ = 150 mA, which is the  
suggested value of bias current for typical applications. For  
special applications such as linear amplification, IDQ may  
have to be selected to optimize the critical parameters.  
The gate is a dc open circuit and draws no current. There-  
fore, the gate bias circuit may generally be just a simple re-  
sistive divider network. Some special applications may  
require a more elaborate bias system.  
Drain  
C
gd  
C
C
C
= C + C  
gd gs  
Gate  
iss  
= C + C  
ds  
C
ds  
oss  
rss  
gd  
= C  
gd  
C
gs  
Source  
GAIN CONTROL  
DRAIN CHARACTERISTICS  
Power output of this device may be controlled to some de-  
gree with a low power dc control signal applied to the gate,  
thus facilitating applications such as manual gain control,  
ALC/AGC and modulation systems. This characteristic is  
very dependent on frequency and load line.  
One critical figure of merit for a FET is its static resistance  
in the full-on condition. This on-resistance, RDS(on), occurs  
in the linear region of the output characteristic and is speci-  
fied at a specific gate-source voltage and drain current. The  
MRF1518NT1 MRF1518T1  
RF Device Data  
Freescale Semiconductor  
14  

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