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MN101EF31D PDF预览

MN101EF31D

更新时间: 2024-11-16 01:07:43
品牌 Logo 应用领域
松下 - PANASONIC 微控制器
页数 文件大小 规格书
9页 467K
描述
8-bit Single-chip Microcontroller

MN101EF31D 数据手册

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MN101E31 Series  
8-bit Single-chip Microcontroller  
Overview  
The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C series) incorporate  
multiple types of peripheral functions. This chip series is well suited for camera, VCR, MD, TV, CD, LD, printer, telephone,  
home automation, pager, air conditioner, PPC, fax machine, music instrument and other applications.  
This LSI brings to embedded microcomputer applications exible, optimized hardware congurations and a simple efcient  
instruction set. The MN101E31 series have an internal 128 KB/64 KB (maximum) of ROM and 6 KB/4 KB(maximum) of  
RAM. Peripheral functions include 6 external interrupts, 23 internal interrupts including NMI, 9 timer counters, 5 sets of serial  
interfaces, A/D converter, LCD driver, watchdog timer, 1 set of automatic data transfer, synchronous output function and buzzer  
output. The conguration of this microcomputer is well suited for application as a system controller in camera, timer selector for  
VCR, CD player, or minicomponent.  
With three oscillation system (high frequency : max. 10 MHz / low frequency : 32.768 kHz and PLL : frequency multiplier  
of high frequency) contained on the chip, the system clock can be switched to high frequency input (high speed mode), PLL  
input (PLL mode), or to low frequency input (low speed mode).  
The system clock is generated by dividing the oscillation clock. The best operation clock for the system can be selected by  
switching its frequency by software. High speed mode has the normal mode which is based on 2-cycle clock (fpll/2) and the  
double speed mode which is based on the not-devided clock with fpll.  
A machine cycle (min. instructions execution) in the normal mode is 200 ns when fosc is 10 MHz (at the time that PLL is  
not used). Amachine cycle in the double speed mode is 100 ns when fosc is 10 MHz. Amachine cycle in the PLL mode is 50 ns  
(maximum).The package is 80-pin, LQFP.  
Product Summary  
This manual describes the following models of the MN101E31 series. These products have identical functions. Please note that mainly  
dealed here is MN101E31G.  
Model  
ROM Size  
RAM Size  
Classication  
Package  
MN101E31G  
MN101E31D  
MN101E31A  
MN101EF31G  
MN101EF31D  
128 KB  
64 KB  
6 KB  
4 KB  
2 KB  
6 KB  
4 KB  
Mask ROM version  
32 KB  
LQFP080-P-1414A  
128 KB + 4 KB  
64 KB + 8 KB  
Flash EEPROM version  
Publication date: February 2012  
Ver. HEM  
1

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