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MN101EF31G PDF预览

MN101EF31G

更新时间: 2024-11-14 22:09:43
品牌 Logo 应用领域
松下 - PANASONIC /
页数 文件大小 规格书
3页 386K
描述
MN101E31G

MN101EF31G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP-80针数:80
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:5.82具有ADC:YES
地址总线宽度:20位大小:8
最大时钟频率:20 MHzDAC 通道:NO
DMA 通道:YES外部数据总线宽度:8
JESD-30 代码:S-PQFP-F80长度:14 mm
I/O 线路数量:70端子数量:80
最高工作温度:85 °C最低工作温度:-40 °C
PWM 通道:NO封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP80,.64SQ
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5/5 V
认证状态:Not QualifiedRAM(字节):6144
ROM(单词):131072ROM可编程性:FLASH
座面最大高度:1.7 mm速度:20 MHz
子类别:Microcontrollers最大供电电压:5.5 V
最小供电电压:2.2 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLER

MN101EF31G 数据手册

 浏览型号MN101EF31G的Datasheet PDF文件第2页浏览型号MN101EF31G的Datasheet PDF文件第3页 
MN101E31G  
Type  
MN101E31G  
MN101EF31G  
Internal ROM type  
ROM (byte)  
Mask ROM  
FLASH  
128K  
4K  
RAM (byte)  
Package (Lead-free)  
LQFP080-P-1414A (Under development)  
50 ns (at 2.2 V to 5.5 V, 20 MHz)  
* at internal 2 , 3 , 4 , 5 , 6 , 8 , 10 times oscillation used  
Minimum Instruction  
Execution Time  
50 ns (at 2.2 V to 5.5 V, 20 MHz)  
Interrupts  
6 external interrupts, 25 internal interrupts  
RESET, Watchdog, External 0 to 4, Timer 0 to 4, Timer 6, Timer 7 (2 systems), Timer 8 (2 systems), Time base, Serial 0 (2 systems),  
Serial1 (2 systems), Serial 2 (2 systems), Serial 3 (2 systems), Serial 4, Serial 5, A/ conversion finish, Automatic transfer, Key  
interrupts  
Timer Counter  
Timer counter 0 : 8-bit × 1  
(timer pulse output, event count, added pulse (2-bit) system PWM output, generation of remote control carrier, simple  
pulse measurement, real time output control)  
Timer counter 1 : 8-bit × 1  
(timer pulse output, event count, 16-bit cascade connected (timer 0, 1) timer synchronous output event)  
Timer counter 2 : 8-bit × 1  
(timer pulse output, event count, added pulse (2-bit) system PWM output, simple pulse measurement, 24-bit cascade  
connected (timer 0, 1, 2), timer synchronous output event, real timer output control)  
Timer counter 3 : 8-bit × 1  
(timer pulse output, event count, generation of remote control carrier, 16-bit cascade connected (timer 2, 3), 32-bit  
cascade connected (timer 0, 1, 2, 3))  
Timer counter 4 : 8-bit × 1  
(timer pulse output, added pulse (2-bit) system PWM output, event count, serial transfer clock, simple pulse  
measurement)  
Timer counter 6 : 8-bit free run timer, time base timer  
Timer counter 7 : 16-bit × 1  
(timer pulse output, event count, High accuracy PWM, High performance IGBT output (cycle/duty continuous variable)  
timer synchronous output event, input capture (Both edge available), real timer output control), double buffer compare  
register  
Timer counter 8 : 16-bit × 1  
(timer pulse output, event count, High accuracy PWM output (cycle/duty continuous variable) pulse width measurement,  
input capture (Both edge available), 32-bit cascade connected (Timer 7 , 8), 32-bitPWM output, synchronous output  
event), double buffer compare register  
Timer counter A : 8-bit × 1 (event count, Serial transfer clock timer, clock for function (timer, serial, LCD))  
Watchdog timer  
Serial interface  
Serial 0 ~ 3 : UART (full duplex) / synchronous × 1  
Serial : multi master I²C / synchronous × 1  
Serial 5 : I²C slave × 1  
DMA controller  
1 systems (External request/internal event request/software request maximum transfer cycles are 255)  
I/O Pins  
I/O  
70  
common use, Specified pull-up/pull-down resistor available, Input/output selectable (bit-unit)  
MAD00064AEM  

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