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MN101EF72D PDF预览

MN101EF72D

更新时间: 2024-11-15 21:22:39
品牌 Logo 应用领域
松下 - PANASONIC 时钟微控制器外围集成电路
页数 文件大小 规格书
9页 495K
描述
Microcontroller, 8-Bit, FLASH, 20MHz, CMOS, PQFP80, 14 X 14 MM, 0.65 MM PITCH, PLASTIC, LQFP-80

MN101EF72D 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:14 X 14 MM, 0.65 MM PITCH, PLASTIC, LQFP-80针数:80
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.8具有ADC:YES
其他特性:ALSO OPERATES AT 2.2 V MINIMUM SUPPLY AT 8 MHZ地址总线宽度:
位大小:8最大时钟频率:20 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:JESD-30 代码:S-PQFP-G80
长度:14 mmI/O 线路数量:52
端子数量:80最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP80,.64SQ封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2.5/3.3 V认证状态:Not Qualified
RAM(字节):2048ROM(单词):65536
ROM可编程性:FLASH座面最大高度:1.7 mm
速度:20 MHz子类别:Microcontrollers
最大供电电压:3.6 V最小供电电压:2.7 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

MN101EF72D 数据手册

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MN101E72 Series  
8-bit Single-chip Microcontroller  
Overview  
The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C series) incorporate  
multiple types of peripheral functions.  
This LSI is provided with a exible and optimized hardware congurations and a simple and efcient instruction system.  
MN101EF72D has an internal 64 KB of ROM and 2 KB of RAM, and equipped with peripheral functions, such as 7 external  
interrupts, 22 internal interrupts including NMI, 8 timer counters, 3-system serial interface, LCD drivers, 16-bit DS A/D  
converter, 12-bit D/A converter, real time clock, watchdog timer, buzzer output, remote control carrier output and thermometry  
providing a system conguration suited for microcomputer for medical equipments, healthcare equipments, or measurement  
systems.  
The LSI also includes 3-system oscillation circuitry (high-speed oscillation of up to 20 MHz, low-speed oscillation of 32  
kHz, and internal ring oscillator), allowing the system clock to be switched among high-speed oscillation input (OSC mode),  
internal ring oscillator input (RING mode), or low-speed oscillation input (SLOW mode).  
The system clock is generated by dividing the oscillation clock frequency. The optimum operation clock for the system can  
be selected by programmatically switching its frequency-dividing ratio. The high-speed mode includes a normal mode which is  
based on a clock (fosc/2) obtained by dividing the original oscillation frequency or internal ring oscillator, by two, and a double-  
speed mode which is based on a clock having the same cycle as the original oscillation (fosc).  
A machine cycle (minimum instruction execution time) is 100 ns when fs is 10 MHz in the normal mode and the double-  
speed mode. Package type is 80-pin LQFP.  
Product Summary  
This datasheet describes the following model.  
Model  
ROM Size  
RAM Size  
Classication  
Package  
MN101EF72D  
64 KB  
2 KB  
Flash EEPROM version  
LQFP080-P-1414A  
Publication date: June 2011  
Ver. AEM  
1

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