Datasheet > MN101EFD3G

MN101EFD3G

更新时间： 2024-11-16 00:58:31

品牌	Logo	应用领域
松下 - PANASONIC		微控制器
页数	文件大小	规格书
46页	519K
描述
8-bit Single-chip Microcontroller

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MN101EFD3G 数据手册

MN101EFC3/D3 Series

8-bit Single-chip Microcontroller

PubNo. 216C3-014E

1.1 Overview

1.1.1

Overview

The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C

series) incorporate multiple types of peripheral functions. This chip series is well suited for in-vehicle

body control, in-vehicle AV, camera, VCR, MD, TV, CD, LD, printer, telephone, home automation,

pager, air conditioner, PPC, fax machine, music instrument and other applications.

This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations

and a simple efficient instruction set.

MN101EFC3D has an internal 76 KB of ROM and 6 KB of RAM. MN101EFC3Y has an internal 76 KB

of ROM and 10 KB of RAM. MN101EFC3G has an internal 128 KB of ROM and 6 KB of RAM.

MN101EFC3Z has an internal 128 KB of ROM and 10 KB of RAM. MN101EFD3D has an internal 76

KB of ROM and 10 KB of RAM. MN101EFD3G has an internal 128 KB of ROM and 10 KB of RAM.

Peripheral functions include 5 external interrupts, 34 internal interrupts including NMI, 12 timer

counters, 4 types of serial interfaces, CAN controller (on MN101EFD3D/G) based on CAN 2.0B, A/D

converter, LCD driver, 2 types of watchdog timer, and data automatic function. The system configura-

tion is suitable for in-vehicle body control microcontroller such as in-vehicle body control, heater control,

relay BOX, or various motor controls.

With 5 oscillation systems (high-speed (internal frequency: 20 MHz), high-speed (crystal/ceramic fre-

quency: max. 10 MHz) / low-speed (internal frequency: 30 kHz), low-speed (crystal/ceramic frequency:

32.768 kHz) and PLL: frequency multiplier of high frequency) contained on the chip, the system clock

can be switched to high-speed frequency input (NORMAL mode), PLL input (PLL mode), or to low-

speed frequency input (SLOW mode). The system clock is generated by dividing the oscillation clock or

PLL clock. The best operation clock for the system can be selected by switching its frequency ratio by

programming. High speed mode has the normal mode which is based on the clock dividing fpll, (fpll is

generated by original oscillation and PLL), by 2 (fpll/2), and the double speed mode which is based on

the clock not dividing fpll.

A machine cycle (minimum instruction execution time) in the normal mode is 200 ns when the original

oscillation fosc is 10 MHz (PLL is not used). A machine cycle in the double speed mode, in which the

CPU operates on the same clock as the external clock, is 100 ns when fosc is 10 MHz. A machine cycle

in the PLL mode and in the double speed mode when the internal oscillation frc is 20 MHz (PLL is not

used) is 50 ns (maximum).

Publication date: November 2015

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与MN101EFD3G相关器件

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MN101EFG0D	PANASONIC	获取价格	8-bit Single-chip Microcontroller
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MN101L	PANASONIC	获取价格	8-Bit MCU with Built-In ReRAM
MN101LR02D	PANASONIC	获取价格	8-bit Single-chip Microcontroller
MN101LR03D	PANASONIC	获取价格	8-bit Single-chip Microcontroller
MN101LR04D	PANASONIC	获取价格	8-bit Single-chip Microcontroller
MN101LR04DXW	PANASONIC	获取价格	8-Bit MCU with Built-In ReRAM
MN101LR05D	PANASONIC	获取价格	8-bit Single-chip Microcontroller
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