Datasheet > MN101EFA1A

MN101EFA1A

更新时间： 2024-11-16 01:04:43

品牌	Logo	应用领域
松下 - PANASONIC		微控制器
页数	文件大小	规格书
33页	818K
描述
8-bit Single-chip Microcontroller

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MN101EFA1A 数据手册

MN101EFA6/A5/A1/A0 Series

8-bit Single-chip Microcontroller

PubNo. 216A6-012E

1.1 Overview

1.1.1

Overview

The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C series)

incorporate multiple types of peripheral functions. This chip series is well suited for automotive power window,

camera, TV, CD, printer, telephone, home appliance, PPC, fax machine, music instrument and other applications.

This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations and a sim-

ple efficient instruction set. MN101EFA6/A5/A1/A0 has an internal 32 KB of ROM and 1 KB of RAM. Periph-

eral functions include 5 external interrupts, including NMI, 8 timer counters, 3 (MN101EFA5/A0: 2) types of

serial interfaces, A/D converter, watchdog timer and buzzer output (MN101EFA5/A0: no buzzer). The system

configuration is suitable for system control microcontroller.

With 2 oscillation systems (internal frequency: 16 MHz, crystal/ceramic frequency: max. 10 MHz) contained on

the chip, the system clock can be switched to high-speed frequency input (NORMAL mode) or PLL input (PLL

mode). The system clock is generated by dividing the oscillation clock or PLL clock. The best operation clock for

the system can be selected by switching its frequency ratio by programming. High speed mode has NORMAL

mode which is based on the clock dividing fpll, (fpll is generated by original oscillation and PLL), by 2 (fpll/2),

and the double speed mode which is based on the clock not dividing fpll.

A machine cycle (minimum instruction execution time) in NORMAL mode is 200 ns when the original oscillation

fosc is 10 MHz (PLL is not used). A machine cycle in the double speed mode, in which the CPU operates on the

same clock as the external clock, is 100 ns when fosc is 10 MHz. A machine cycle in the PLL mode is 50 ns (max-

imum).

1.1.2

Product Summary

This manual describes the following model.

Table:1.1.1 Product Summary

Capacitive Touch

Detection Circuit

Model

ROM Size RAM Size

Classification

Package

MN101EFA6A

MN101EFA1A

MN101EFA5A

MN101EFA0A

32 KB

1 KB

Flash EEPROM version



44-Pin QFP

48-Pin TQFP



32-Pin SSOP

32-Pin TQFP

Publication date: November 2014

12 3 4 5 6 7...33

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